One transistor cell FeRAM memory array

Details One transistor cell FeRAM memory array One transistor cell FeRAM memory array

2002-10-28

2004-03-23

Tran, M. (Department: 2818)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S129000

Reexamination Certificate

active

06711049

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to non-volatile memory, and specifically to a single transistor ferroelectric random access memory (FeRAM) memory array.
BACKGROUND OF THE INVENTION
Flash memory and EEPROM are the state-of-the-art single transistor non-volatile memory cells. The programming of these devices requires high voltage and a high-power electrical pulse, which causes electrons to tunnel through a thin gate oxide present in these devices, or which create “hot” electrons, which may hop over an oxide energy barrier to a floating gate.
SUMMARY OF THE INVENTION
A one-transistor FeRAM memory cell array includes an array of ferroelectric transistors arranged in rows and columns, each transistor having a source, a drain, a channel, a gate oxide layer over the channel and a ferroelectric stack formed on the gate oxide layer; word lines connecting the gate ferroelectric stack top electrodes of transistors in a row of the array; a connection to the channel of all transistors in the array formed by a substrate well; a set of first bit lines connecting the sources of all transistors in a column of the array; and a set of second bit lines connecting the drains of all transistors in a column of the array; wherein the ferroelectric stack has opposed edges, which, when projected to a level of the source, drain and channel, are coincident with an abutted edge of the source and the channel and the drain and the channel, respectively.
An object of the invention is to provide an array of ferroelectric non-volatile single transistor memory cells in a for random access memory application.
Another object of the invention is to provide a FeRAM which uses a programming voltage approximately less than two times that of the operating voltage.
A further object of the invention is to provide a FeRAM array which is compatible with state of the art ULSI technology and which is scalable to very low voltage operation.
Another object of the invention is to provide a modified array having a low power dissipation during a write operation.


REFERENCES:
patent: 6370056 (2002-04-01), Chen et al.
patent: 6510073 (2003-01-01), Lee et al.

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