Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus access regulation
Reexamination Certificate
1998-10-30
2001-10-16
Lee, Thomas (Department: 2182)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus access regulation
C710S052000, C710S054000, C710S057000, C710S037000, C710S112000, C710S113000, C370S463000, C370S412000, C370S414000
Reexamination Certificate
active
06304936
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to computer buses and computer networks. More particularly, the invention relates to a one-to-many bus bridge that employs a multiple logical FIFO system to improve bandwidth efficiency and to reduce hardware size and cost.
BACKGROUND
A bus bridge is used to interface different types of computer buses. For example, in a conventional computer, CPUs and system memory may be coupled to one another via a high-speed system bus. Input output (“I/O”) devices, on the other hand, may be coupled to a slower-speed I/O bus. In such an architecture, the system bus and the I/O bus are typically interfaced by means of a bus bridge. The function of such a bus bridge generally is to handle the translation of speeds and protocols in such a manner that bus cycles may occur on either side of the bridge in relatively independent fashion.
A first-in-first-out or “FIFO” buffer is a well-known memory tool often used to transfer data from a source system to a destination system wherein the rate of output from the source system is not always the same as the rate of input of the destination system.
One of the challenges presented in the design of bus bridges is to provide adequate FIFO buffering to accommodate the speed differences between a system bus and I/O buses without unduly increasing system cost and complexity. For example, assume an architecture in which programmed I/O cycles (“PIO cycles”) originating from a CPU on a system bus may be destined for any one of n different I/O buses depending on the addresses involved in each cycle. One method of handling such an architecture in the bus bridge design is to provide n separate conventional FIFO buffers, one for each of the n destination I/O buses. Each PIO cycle originating on the system bus may then be placed in the FIFO buffer that corresponds to that cycle's destination I/O bus.
Assume further that flow control on the system bus is indirect in the sense that, once the bus bridge indicates an I/O halt condition, numerous forthcoming PIO cycles may yet need to be processed by the bus bridge before all PIO cycles cease to issue from the system bus. In such a circumstance, the bus bridge cannot know in advance to which I/O buses these post-halt PIO cycles will be destined. A designer must therefore assume the worst-case scenario—that all of the post-halt PIO cycles will be destined for the I/O bus having the fullest FIFO buffer at the time the I/O halt indication is given.
The result of this assumption is deleterious in at least two ways: First, it means that, as a rule, an I/O halt indication must be issued by the bus bridge whenever any one of its n FIFO buffers reaches a state in which the buffer would be completely filled should all post-halt PIO cycles be destined for it. Such a rule would be unfortunate from a bandwidth efficiency standpoint if the worst-case scenario occurs only rarely. Second, it means that the aggregate FIFO storage capacity in the bus bridge will be wasted because no more than one of the FIFO buffers could ever become completely full in a system that operates under such a rule.
It is therefore an object of the present invention to provide a one-to-many bus bridge design in which FIFO storage capacity is used in a manner that improves bandwidth efficiency and reduces circuit size and cost.
SUMMARY OF THE INVENTION
The invention includes numerous aspects, each of which contributes to achieving the above-recited objectives.
In a first aspect, a one-to-many bus bridge includes a system bus interface, a first I/O bus interface, a second I/O bus interface, a multiple logical FIFO system wherein first and second logical FIFOs share a common storage system, and demultiplexer and control circuitry. The demultiplexer and control circuitry are configured so that cycle information destined for the first I/O bus interface is enqueued from the system bus interface into the first logical FIFO and is dequeued from the first logical FIFO into the first I/O bus interface. Cycle information destined for the second I/O bus interface is enqueued from the system bus interface into the second logical FIFO and is dequeued from the second logical FIFO into the second I/O bus interface.
In another aspect, the bus bridge further includes a level-of-fullness monitor for monitoring the level of fullness of the common storage system in the multiple logical FIFO system. The level-of-fullness monitor generates first and second level-of-fullness indications depending on the amount of storage capacity remaining in the common storage system at a given point in time. The system bus interface further comprises a flow control input and is operable to declare I/O halt and I/O resume conditions on a system bus responsive to halt and resume commands, respectively, on the flow control input. The control circuitry issues the halt command when the first level-of-fullness indication is generated, and it issues the resume command when the second level-of-fullness indication is generated. Preferably, the first level-of-fullness indication is generated before the free storage capacity in the common storage system becomes less than a predetermined maximum size of post-halt cycle information that may come in through the system bus interface after an I/O halt condition is asserted. The second level-of-fullness indication may be generated after the amount of free storage capacity in the common storage system becomes greater than the predetermined maximum size of the post-halt cycle information.
In another aspect, the multiple logical FIFO system of the bus bridge uses a single main register file to store payload data in association with link data so as to form one linked list data structure for each logical FIFO in the system. A write pointer register file stores one write pointer for each logical FIFO. A read pointer register file stores one read pointer for each logical FIFO. A free register identifier indicates a free register address at all times unless the overall system is full. The free register address corresponds to one free register within the main register file. When a word of write data is to be enqueued into a logical FIFO, the following actions occur: An active write pointer register is selected within the write pointer register file responsive to a write FIFO number input. A destination register is selected within the main register file responsive to the contents of the active write pointer register. The word of write data is loaded into a payload data field of the destination register. And the free register address is loaded into both the active write pointer register and the link data field of the destination register. Thus, after the word of write data has been enqueued into a logical FIFO, it is stored in the main register file in association with a pointer to a new register in the main register file. The new register will be used to store the next data word for that logical FIFO. In order to ensure this result, the address of the new register has been loaded into the write pointer register corresponding to that logical FIFO. When a word of read data is to be dequeued from a logical FIFO, the following actions occur: An active read pointer register is selected within the read pointer register file responsive to a read FIFO number input. A source register is selected within the main register file responsive to the contents of the active read pointer register. The word of read data is routed from the payload data field of the source register to the read data output. And the contents of the link data field of the source register are loaded into the active read pointer register. Thus, after the word has been dequeued, the read pointer for that logical FIFO has been updated to point to the next oldest data in the FIFO.
In yet another aspect, the free register identifier may contain an array of storage cells, wherein each storage cell of the array corresponds to one of the registers within the main register file. The state of each storage cell is maintained to indicate whether the corresponding register in the
Hart Kevin M.
Hewlett--Packard Company
Lee Thomas
Schuster Katharina
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