One time programmable fully-testable programmable logic device w

Details One time programmable fully-testable programmable logic device w One time programmable fully-testable programmable logic device w

1996-05-24

2000-11-14

Santamauro, Jon

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 16, 326 38, 326 49, 327525, H03K 19173

Patent

active

RE0369527

ABSTRACT:
There is a zero power programmable logic device with a one time programmable and fully-testable anti-fuse cell architecture. Specifically, a half-latch and fuse cell circuit allows the PLD to use "zero power" during the standby period since the sense amps are not used to maintain the programmed logic. Additionally, the PLD is capable of being tested for logic gate and logic path integrity, and anti-fuse electrical parameters without permanently programming the anti-fuse.

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