Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-02-21
2003-08-05
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S655000, C438S657000, C438S664000
Reexamination Certificate
active
06602786
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a semiconductor manufacturing process and more specifically relates to a process for forming a low resistance titanium silicide layer atop a polysilicon layer to reduce the lateral resistance of the polysilicon layer.
BACKGROUND OF THE INVENTION
Semiconductor devices, such as power MOSFETs, IGBTs, and the like commonly have thin layers of polysilicon used, for example, as gate electrodes. It is desirable to reduce the lateral resistance of these polysilicon layers and they are commonly doped by impurities such as phosphorous to increase their conductivity. It is also known to further coat the top of the polysilicon layer with a titanium silicide layer of low resistivity.
To obtain this low resistivity titanium silicide layer, a two-step rapid thermal anneal (RTA) process, each at temperature less than about 750° C., is used. The thermal processing should be a temperature less than about 800° C. at which contamination diffusion begins. However, the underlying silicon remains completely clean if the RTA temperature is no greater than 625° C. The use of titanium silicide for this purpose is described in the following: J. Lutze, G. Scott, and M. Manley, “Transistor off-state leakage current induced by TiSi2 pre-amorphizing implant in a 0.20 um CMOS process,”
IEEE Trans. Electron Device Lett.,
vol. 20, p. 155, April 2000; Qingfeng Wang, “TiSi2 and CoSi2 SALICIDE Technology and their Application in CMOS,” Advanced Process Technology Seminar, AG Associates, Jun. 20 and 21, 1996; J. F. DiGregorio and R. N. Wall, “Small Area Versus Narrow Line Width Effects on the C49 to C54 Transformation of TiSi2,”
IEEE Trans. Electron Devices,
vol. 47, p. 313, February 2000; C. Y. Chang and S. M. Sze, “ULSI Technology,” The McGraw-Hill Companies, Inc., 1996, ISBN 0-07-063062-3; and S. P. Murarka, “Silicide for VLSI Applications,” Academic Press, Inc., 1983, ISBN 0-12-11220-3.
It would be desirable to deposit a low resistivity layer of titanium silicide on polysilicon using a single RTA step.
BRIEF SUMMARY OF THE INVENTION
In accordance with the invention, a titanium silicide layer is formed atop a polysilicon layer surface with a single low temperature (under 650° C.) RTA step. Thus, an intermediate amorphous silicon layer is first formed atop the polysilicon. Titanium is then sputtered atop the amorphous silicon layer, and a single RTA step is carried out at about 625° C. for about 30 seconds, followed by a titanium wet strip, producing the desired low resistivity titanium silicide layer intimately bonded to the polysilicon layer.
REFERENCES:
patent: 6015753 (2000-01-01), Lin et al.
patent: 6015997 (2000-01-01), Hu et al.
patent: 6033978 (2000-03-01), Fujii et al.
patent: 6107154 (2000-08-01), Lin
patent: 6284635 (2001-09-01), Jang
Dang Trung
International Rectifier Corporation
Ostrolenk Faber Gerb & Soffen, LLP
LandOfFree
One-step process for forming titanium silicide layer on... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with One-step process for forming titanium silicide layer on..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and One-step process for forming titanium silicide layer on... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3102463