Radiation imagery chemistry: process – composition – or product th – Imaging affecting physical property of radiation sensitive... – Making electrical device
Reexamination Certificate
2000-01-18
2002-03-12
Baxter, Janet (Department: 1752)
Radiation imagery chemistry: process, composition, or product th
Imaging affecting physical property of radiation sensitive...
Making electrical device
C430S313000, C430S005000
Reexamination Certificate
active
06355399
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of creating a dual damascene structure using one processing step of patterning this structure.
(2) Description of the Prior Art
The manufacturing of semiconductor devices requires the application of multiple diverse technical disciplines that collectively enable the continuing advancements of device performance that has been accomplished ever since the initiation of the semiconductor device. These various disciplines address various aspects of the device creation whereby typically a plurality of active circuits is created in a semiconductor substrate. To create a collection of circuits, commonly referred to as Integrated Circuits (IC's), the individual circuits are interconnected with metal leads. To further increase device density, multiple layers of interconnect metal can be created. These multiple layers of interconnect metal are separated by layers of dielectric or by insulating layers. Adjacent layers of metal lines are interconnected by means of metal contact plugs or vias.
The semiconductor industry has, over the last several decades, been driven by a continued striving to improve device performance, which requires a continued decrease of semiconductor device feature size. In present day semiconductor devices, it is not uncommon to encounter feature size in the deep sub-micron range. With this decrease in device feature size, sub-micron metal interconnects become increasingly more important. A number of different approaches are used in the art for the formation of patterns of interconnect lines, most of these approaches start with the deposition of a patterned layer of dielectric where the pattern in the dielectric forms contact openings between overlying metal and underlying points of electrical contact. A layer of metal is deposited over the layer of dielectric and patterned in accordance with the required pattern of interconnect lines whereby the interconnect lines, where required, align with the underlying contact openings. The patterning of the layer of metal requires the deposition of a layer of photoresist over the layer of metal, the photoresist is exposed typically using photolithographic techniques and etched, typically using a dry etch process. The patterned layer of photoresist is removed after the interconnect metal line pattern has been created leaving the interconnect line pattern in place. For sub-micron metal line sizes, these highlighted processing steps encounter a number of problems that are typical of device sub-miniaturization. These problems are problems of poor step coverage of the deposited metal (the metal should be evenly deposited and should fill the profile for the metal line with equal metal density), problems of etching (using dry etching but metal such as copper and gold are difficult to plasma etch) and problems of step coverage and planarization for the overlying layer of dielectric.
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings. The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level. The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contacts. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers, these openings are filled with metal whereby the openings between the two metal layers are lined up with and match contact points in one or both of the levels of metal lines.
The brief description of the process of metalization that has been given above has been described with reference to the damascene and dual damascene processes which form two widely used approaches in creating metal interconnects. The application of the damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale Integrated (ULSI) devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices.
With increasing device densities, the area that is available for circuit wiring becomes relatively more important as a potential limiting factor in device performance. This has led to the development of multi-layer wiring where the dual damascene structure has found wide use.
For the creation of the single damascene structure, vias only are created. For the creation of the dual damascene, vias are created and conductors are created above the vias. For the dual damascene, special etch procedures can be used to form both the vias and the conductor patterns in the dielectric layer before the deposition of metal and the metal CMP. A thin etch stop layer can be used for this purpose between two layers of dielectric SiO
2
.
With the damascene process a metal via plug is first formed in a surface, typically the surface of a semi-conductor substrate. A layer of dielectric (for instance SiO
2
) is deposited over the surface (using for instance PECVD technology); trenches (for metal lines) are formed in the dielectric (using for instance RIE technology). Metal is deposited to fill the trenches; the excess metal on the surface is removed. A planar structure of interconnect lines with metal inlays in the (intra-level) dielectric is achieved in this manner.
For the dual damascene process, the processing steps can follow three approaches.
Approach 1, the via is created first. The vias are formed by resist patterning after which an etch through the triple layer dielectric stack is performed. This is followed by patterning the conductor in the top layer of SiO
2
thereby using the SiN as an etch stop layer.
Approach 2. The conductor first process. The conductor patterns is formed by resist patterning and by etching the conductor patterns into the first SiO
2
layer thereby using the SiN layer as an etch stop layer. This is followed by via resist patterning and etching through the thin layer of SIN and the second SiO
2
layer.
Approach 3. Etch stop layer first. The first SiO
2
layer is deposited, followed by the thin layer of SiN as etch stop, followed by the via resist patterning and etching of the SiN layer. This is followed by depositing the top SiO
2
layer and then the conductor patterning. In etching the conductor pattern in the top SiO
2
layer, the etching process will be stopped by the SiN layer except where the via holes are already opened in the SiN layer thereby completing the via holes etching in the first SiO
2
layer simultaneously.
FIGS. 1
a
and
1
b
further detail the above.
FIG. 1
a
gives and overview of the sequence of steps required of forming a Prior Art dual Damascene structure. The numbers referred to in the following description of the formation of the dual Damascene structure relate to the cross section of the completed dual Damascene structure that is shown in
FIG. 1
b.
FIG. 1
a
,
21
shows the creation of the bottom part of the dual Damascene structure by forming a via pattern
22
on a surface
24
, this surface
24
can be a semiconductor wafer but is not limited to such. The via pattern
22
is created in the plane of a dielectric layer
20
and forms the lower part of the dual Damascene structure. SiO
2
can be used for this dielectric.
FIG. 1
a
,
22
shows the deposition within plane
30
(
FIG. 1
b
) of a layer of non-metallic material such as poly-silicon on top of the first dielectric
20
and across the vias
22
, filling
Cheng Tsun-Lung Alex
Hua Zhu Sui
Sajan Marokkey Raphael
Chartered Semiconductor Manufacturing Ltd.
Pike Rosemary L. S.
Saile George O.
Walke Amanda C.
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