One or two transistor logic with temperature compensation and mi

Details One or two transistor logic with temperature compensation and mi One or two transistor logic with temperature compensation and mi

1994-04-06

1995-01-17

Hudspeth, David R.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Bipolar and fet

326112, 326124, 327543, H03K 1716

Patent

active

053828437

ABSTRACT:
The logic ensures a smallest achievable propagation delay, lowest achievable supply voltage and low power consumption. Silicon or GaAs can be used. The gain of each gate is preferably low. A local supply voltage E depends on temperature and is provided for each gate or plurality of gates fabricated on a single chip. The main supply voltage V-, whose variations are insignificant, may be as small as -1 V or -0.5 V if bipolar transistors or FETs are used respectively. An inverter may comprise merely one transistor with the source coupled to E. A or a second transistor is coupled between the drain of the first transistor and ground. A binary input voltage is applied to the gate of the first transistor. A binary output voltage appears at the drain and is independent of temperature. An n-input NOR gate is established simply by adding n-1 transistors in parallel with the first transistor.

REFERENCES:
patent: 4242604 (1980-12-01), Smith
patent: 4340867 (1982-07-01), Sano
patent: 4350906 (1982-09-01), Gillberg
patent: 4473762 (1984-09-01), Iwahashi et al.
patent: 4491747 (1985-01-01), Shimizu
patent: 4713560 (1987-12-01), Herndon
patent: 5023480 (1991-06-01), Gieseke et al.
patent: 5045727 (1991-09-01), Danckaert et al.
patent: 5065057 (1991-11-01), Kawasaki

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