One-hot decoded phase shift prescaler

Details One-hot decoded phase shift prescaler One-hot decoded phase shift prescaler

1999-11-03

2003-05-27

Vo, Don N. (Department: 2631)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S375000, C375S376000, C327S113000, C327S151000, C327S152000, C327S153000, C327S160000, C327S162000

Reexamination Certificate

active

06570946

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention is generally related to frequency synthesis circuits. More particularly, the present invention is related to a dual-modulus prescaler using a one-hot decoded phase shift circuit.
Frequency synthesizers are an important building block of transceivers in radio devices. The frequency synthesizer is used to generate the local oscillator signal for demodulating received radio signals and modulating signals for transmission. For ideal performance of the transceiver, the frequency synthesizer and its component parts must operate at high precision. Since many modern radios are portable devices, small size and minimal current design are further design goals for a frequency synthesizer.
Conventional frequency synthesizers employ a phase locked loop (PLL), illustrated in
FIG. 1
, for tracking output frequency with an input, high precision oscillator frequency. Along with a prescaler
102
, the PLL
100
typically includes a phase detector
104
, a voltage controlled oscillator (VCO)
106
and a loop filter
108
. A reference frequency labeled fref in
FIG. 1
is received at an input
110
and the output signal at frequency fout is provided at an output
112
. The prescaler
102
divides the frequency of the output signal from the VCO
106
by a variable division ratio to a certain low frequency. The low frequency signal is locked by the PLL
100
onto a very stable reference frequency, fref. A mode signal is provided at a mode input
114
of the prescaler
102
to select a modulus of division.
The prescaler
102
must include the logic necessary to select the desired modulus. The added dual modulus logic slows the operation of the prescaler
102
and even limits the upper frequency of operation of the prescaler
102
and the PLL
100
. The prescaler
102
and the VCO
106
are the only blocks in the PLL
100
operating at the full frequency fout of the output signal. In a radio such as a cellular telephone, this frequency is in the range of 800 MHz and 2.0 GHz.
One improved prescaler design has been proposed by Craninckx and Steyaert in 1.75 Ghz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7 &mgr;m CMOS, IEEE Journal of Solid-State Circuits, &mgr; 31, no. 7, July 1996, page 890.
FIG. 2
illustrates this prescaler
200
.
The prescaler
200
includes an input buffer
202
, a divide by two block
204
, a divide by two block
206
, a phase rotator
208
, a divide by (n/4) block
210
, a logic gate
212
and a frequency control circuit
214
. The input buffer
202
receives a differential signal, labeled VCO_Clk+ and VCO_Clk− in FIG.
2
. This signal is buffered to suitable logic levels and passed to a clock input of the divide by two block
204
. The divide by two block
204
is any suitable divider such as a D-flip flop. The output of the divide by two block
204
is fed back to the input of the block
204
and also to the clock input of the divide by two block
206
. The divide by two block
206
is configured as a master-slave flip flop and provides two differential output signals. The output signal of the slave flip flop is provided as the differential output labeled SQ and SQB in FIG.
2
. This output signal is fed back to the input of the divide by two block
206
, labeled D and DB. The output of the master flip flop is provided as the differential output labeled MQ and MQB in FIG.
2
.
The four outputs from the master slave flip flop provide four quadrature signals. Each of the signals SQ, SQB, MQ and MQB is related to the input signal by a phase shift that is a multiple of 90 degrees. Thus, quadrature signals having phases 0 degrees, 90 degrees, 180 degrees and 270 degrees different from the input signal are available.
The phase rotator
208
selects one of the quadrature signals and passes the selected signal to the divide by (n/4) circuit
210
. The selection is made based on an input signal from the frequency control circuit
214
. This provides a divide by N operation. The output signal from the divide by (n/4) circuit
210
is the output signal from the prescaler
200
. This output signal is passed to the logic gate
212
, which is gated by a mode signal received at a mode input
216
. Once a modulus or mode signal is provided to the mode input
216
, an output edge signal from the divide by (n/4) circuit
210
provides a reference to switch phases for an N+1 division operation through the feedback path of logic. Thus, the mode signal disables and enables the feedback path to perform the needed N and N+1 frequency division ratio of the prescaler.
The feedback path of the phase shifting prescaler
200
is the critical path of this circuit. The feedback path includes the logic gate
212
and the frequency control circuit
214
. The propagation delay through this circuit will limit the maximum operation frequency of the prescaler
200
and of any PLL and frequency synthesizer utilizing the prescaler
200
.
FIG. 3
illustrates one proposed circuit
300
for implementing the frequency control circuit
214
. The circuit
300
includes a first switchable amplifier
302
, a second switchable amplifier
304
and a multiplexer
306
. By finding the sum or difference of the signals received at the switchable amplifiers
302
,
304
the circuit
300
obtains the four necessary quadrature phase signals. To implement the proper sequence of signals for controlling the amplifiers
302
,
304
, the input signals labeled C
1
and C
2
are tied together to obtain 0 and 90 or 180 and 270 degree phase shifts of the intended signal. The control line labeled CO selects between the 0 or 90 and 180 or 270 degree phases of the intended signal. A two bit counter or other logic circuit is necessary in the feedback path for frequency control.
FIG. 4
illustrates a two bit counter
400
suitable for controlling the frequency control circuit
300
of FIG.
3
. The counter
400
includes a D flip flop
402
, an exclusive OR gate
404
, a D flip flop
406
and an exclusive OR gate
408
. The counter receives a clock signal at an input
410
and provides a two bit output, including a most significant bit (MSB) at output
412
and least significant bit (LSB) at output
414
. The table in
FIG. 4
illustrates the counter sequence that allows phase shifting to occur in the control circuit
300
of
FIG. 3
used in the prescaler
200
of FIG.
2
.
FIG. 5
is a plot of voltage versus time displaying proper operation of the prescaler
200
using the circuit
300
and the counter
400
for a divide by N+1 operation.
FIG. 5
shows a first signal
502
and a second signal
504
along with the output signal
506
of the PLL. The second signal
504
lags the first signal
502
by a 90 degree phase shift.
The major short coming of the circuitry of
FIGS. 3 and 4
is a possibility of glitches on the output signal
506
. This may be more properly referred to as a metastable state. A metastable state is a concern because its presence may cause an incorrect frequency division and will cause the PLL using the prescaler to become consistently unlocked from its designed local oscillator frequency. Also, metastability at the output of the switchable amplifiers
302
,
304
of
FIG. 3
could cause improper division by the divide by (n/4) circuit
210
in the prescaler
200
of FIG.
2
. This results in a large amount of phase noise in the frequency synthesizer employing the prescaler
200
.
FIG. 6
is a plot of voltage versus time displaying signals of the prescaler
200
of
FIG. 2
when a metastable state occurs. The metastable state occurs when the switchable amplifier
302
,
304
switches abruptly in an unsafe switching region to cause metastability as shown in FIG.
6
. The metastability is manifested as glitches
602
,
604
in the output signal
506
.
FIG. 7
is a plot of voltage versus time displaying signals of the prescaler
200
of FIG.
2
. In
FIG. 7
illustrates times when the phase shifting prescaler
200
may safely switch to avoid the metastable state. In the illustrated example, a prescaler operating at 2.5 GHz has a phase delay o

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