One-device random access memory cell having enhanced capacitance

Details One-device random access memory cell having enhanced capacitance One-device random access memory cell having enhanced capacitance

1983-01-31

1985-09-17

Popek, Joseph A.

Static information storage and retrieval

Systems using particular element

Capacitors

357 41, G11C 1124

Patent

active

045424810

ABSTRACT:
An improved one-device random access memory cell comprises a transistor and a capacitor, with one of the transistor's controlled electrodes being connected to one of the capacitor plates to form a storage node. The storage node is maintained at either a first or a second voltage level depending upon the binary state of the cell.
The other capacitor plate is connected to a voltage level which is approximately midway between the first and second voltage levels so that the maximum voltage across the capacitor is reduced to one half the voltage of prior art cells wherein the other capacitor plate was grounded or maintained at the memory power supply voltage level. By halving the maximum voltage across the capacitor, the capacitor dielectric thickness may be halved to thereby double the capacitance per unit area without exceeding the capacitor dielectric breakdown field strength.

REFERENCES:
patent: 4141027 (1979-02-01), Baldwin et al.
patent: 4163243 (1979-07-01), Kamins et al.
patent: 4164751 (1979-08-01), Tasch, Jr.
patent: 4225945 (1980-09-01), Kuo
patent: 4240092 (1980-12-01), Kuo
patent: 4259729 (1981-03-01), Tokushige
patent: 4423490 (1983-12-01), Roesner
IBM Technical Disclosure Bulletin, vol. 19, No. 2, Jul. 1976, "One-Device Storage Cell with Implanted Storage Node", S. P. Klepner, pp. 458-459.

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