One device field effect transistor (FET) AC stable random access

Details One device field effect transistor (FET) AC stable random access One device field effect transistor (FET) AC stable random access

1979-12-26

1982-03-09

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

357 45, 365 72, G11C 1124, G11C 1140, G11C 510

Patent

active

043193420

ABSTRACT:
Disclosed is an integrated circuit electrode memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region in and out of the capacitive storage region. Each memory cell also has a bit line contact region which is shared with an adjacent memory cell. The word lines are arranged in rows in a substantially equidistant parallel relationship, each word line passing, in succession, over the storage region of a first one of the memory cells and electrically integral with the gate region of a second one of the memory cells. The column arrangement of memory cells is interdigitated such that the memory cells associated with a single bit line are arranged in first and second parallel lines along both the left and right sides of each bit line. Thus, the bit line is arranged in a zig-zag configuration alternatively contacting memory cells arranged along its left and right side.

REFERENCES:
patent: 3387286 (1968-06-01), Dennard
patent: 4044340 (1977-08-01), Itoh
patent: 4103347 (1978-07-01), Barton
Itoh et al., "A High-Speed 16 K Bit HMOS Random Access Memory", IEEE J. Solid-State Circuits, SC-11, pp. 585-590, 10/76.

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