Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Patent
1998-04-16
2000-12-26
Lintz, Paul R.
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
G06F 102
Patent
active
061675601
ABSTRACT:
A method for selecting the state assignments of a complex programmable logic device (CPLD) to minimize power consumption. Within the CPLD, a plurality of macrocells are selected to store a corresponding plurality of state variables, wherein the number of macrocells is selected to be equal to the number of states. For each of the states, one of the macrocells is assigned to store a state variable having a first logic state, and the remaining macrocells are assigned to store state variables having a second logic state. The macrocells storing state variables having the second logic state exhibit a lower power consumption than the macrocell storing the state variable having the first logic state. In addition, each of the macrocells includes a plurality of wired logic gates, each being in a high-current state or a low-current state. The number of wired logic gates in the low-current state is maximized in the macrocells assigned to store the state variables having the second logic state. As a result of these state assignments, the CPLD exhibits a relatively low power consumption.
REFERENCES:
patent: 4774421 (1988-09-01), Hartmann
patent: 5388248 (1995-02-01), Robinson
patent: 5481484 (1996-01-01), Ogawa
patent: 5642404 (1997-06-01), Simpson
"The ISP Application Guide and CPLD Data Book", (May 1997) pp. 3-1 to 3-67, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Jenkins, IV Jesse H.
Young Edel M.
Do Thuan
Hoffman, Esq. E. Eric
Lintz Paul R.
Xilinx , Inc.
Young Edel M.
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