One-chip microcomputer and method of refreshing its data

Details One-chip microcomputer and method of refreshing its data One-chip microcomputer and method of refreshing its data

2000-02-14

2002-07-02

Nguyen, Than (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S101000, C711S102000, C711S104000, C711S106000, C711S115000, C365S185080, C365S185090, C365S185220

Reexamination Certificate

active

06415352

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a one-chip microcomputer containing a nonvolatile memory of which the data is electrically erasable, and a method for refreshing data in the one-chip microcomputer. More particularly, the invention relates to the improvement of a data retaining characteristic of a nonvolatile memory.
FIG. 8
is a view showing a cell structure in a nonvolatile memory, generally used, of the split gate type when it is in a programmed state. In the figure, reference numeral
1
is a control gate;
2
is a floating gate;
3
is a drain; and
4
is a source.
To set up a programmed state (i.e. programming mode) in the nonvolatile memory of
FIG. 8
, 2V, 0V and 12V are applied to the control gate
1
, the drain
3
and the source
4
of the nonvolatile memory, respectively. In the cell structure, the control gate
1
and the floating gate
2
are capacitively coupled with each other, and the floating gate
2
and the source
4
are also capacitively coupled with each other (capacitance between the control gate
1
and the floating gate
2
<capacitance between the floating gate
2
and the source
4
). With such voltage application, because of a coupling capacitance ratio, the floating gate
2
is put in a state equivalent to a state that it is under high voltage of, for example, 11V, although no voltage is actually applied to the floating gate
Under this condition, a channel which is continuous for electrons is formed between the drain
3
and the source
4
. Hot electrons in the channel are injected into the floating gate
2
through an insulating film (not shown), so that the floating gate
2
is put in a state that it is negatively charged. This state is a programmed state of the nonvolatile memory.
FIG. 9
shows a cell structure showing a reading state of the nonvolatile memory when it is in a programmed state.
FIG. 10
shows a cell structure showing a reading state of the nonvolatile memory when it is in a non-programmed state.
When the rading state is to be set in either of the nonvolatile memories of
FIGS. 9 and 10
, 5V, 2V and 0V, for example, are respectively applied to the control gate
1
, the drain
3
and the source
4
. In the cell structure of
FIG. 9
, electrons have been injected into the floating gate
2
. Accordingly, no channel is formed between the drain
3
and the source
4
, and the nonvolatile memory cell is turned off. In the cell structure of
FIG. 10
, no electrons are present in the floating gate
2
. Accordingly, a channel is formed between the drain
3
and the source
4
, and the nonvolatile memory cell is turned on.
FIG. 7
is a block diagram showing a circuit for outputting a binary logic value “0” or a binary logic value “1” in accordance with a programmed state of the nonvolatile memory cell. In the figure, reference numeral
5
is a nonvolatile memory cell and numeral
6
is a sense amplifier. The sense amplifier
6
outputs a voltage signal of 0V (binary logic value “0”) or a voltage signal of 5V (binary logic value “1”) in accordance with the result of comparing an output current (read current) of the nonvolatile memory cell
5
with a reference current Iref.
When the nonvolatile memory cell
5
is placed in a programmed state as shown in
FIG. 9
, the sense amplifier
6
senses that the output current (read current) of the nonvolatile memory cell
5
is smaller than the reference current Iref, and outputs a binary logic value “0”. When the nonvolatile memory cell
5
is in a non-programmed state as shown in
FIG. 10
, the sense amplifier
6
senses that that the output current (read current) of the nonvolatile memory cell
5
is larger than the reference current Iref, and outputs a binary logic value “1”. When the reference current drops to a value 30% of 100 &mgr;A as an initial value in a state that the nonvolatile memory cell
5
is in a non-programmed state (the erasing state), it is judged, by convention, that the memory cell reaches the lower limit of data rewriting operation margin or its life has terminated.
FIG. 11
is a diagram showing a cell structure showing an erasing state of the nonvolatile memory. When 14V is applied to the control gate
1
, and 0V is applied to the drain
3
and the source
4
, then electrons that are injected into the floating gate
2
migrate to the control gate
1
through the insulating film. In this case, no channel is formed since the drain
3
and the source
4
are at the equal potential. This state is the erasing state of the nonvolatile memory.
As described above, in the conventional nonvolatile memory, the fixed voltages are applied to the control gate
1
, the drain
3
and the source
4
for fixed times in accordance with the programmed state, the reading state, and the erasing state of the nonvolatile memory.
In the one-chip microcomputer containing the thus constructed nonvolatile memory, when the nonvolatile memory is used in the form of a ROM, the data retaining characteristic of the memory is of great significant.
Particularly in a memory cell array structure shown in
FIG. 12
, voltage application conditions for a non-select cell encircled by a dotted line are the same as in the erasing state mentioned above except an amplitude of voltage (5V) applied to control gates
1
(word line WL) (in this cell array structure, the voltage applied thereto is 14V as mentioned above).
In the memory cell array structure, when the reading operation is repeated, the electrons that are charged into the floating gate
2
will creep to the control gate
1
, possibly causing a reading failure. In particular in a case where a power source voltage is high, the electron creeping is remarkable.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a one-chip microcomputer which improves the data retaining characteristic of the memory by rewriting data into the nonvolatile memory before a reading failure occurs, and a method of refreshing data in the one-chip microcomputer.
The present invention has been made to solve the above problems, a rewriting-number counter for counting the number of data rewriting operations is provided for each nonvolatile memory
7
. When the count value of the counter reaches a desired value, data that is stored in the nonvolatile memory
7
is rewritten into the nonvolatile memory, whereby the data retaining characteristic of the memory is improved.
Further, reference nonvolatile memory groups
40
which are inferior in characteristics to a nonvolatile memory
7
in the memory cell array are provided. Under control of a control circuit
44
, data that is stored in the nonvolatile memory
7
is rewritten into the memory in accordance with the result of referring to the nonvolatile memory groups
40
, whereby the data retaining characteristic of the memory is improved. The reference nonvolatile memory groups
40
have each a cell structure of which the gate length is longer than or the gate width is shorter than of an internal nonvolatile memory
7
. The reference nonvolatile memory groups
40
are all put in a programmed state (“0” state).


REFERENCES:
patent: 6075723 (2000-06-01), Naiki et al.
patent: 6151246 (2000-11-01), So et al.
patent: 6208560 (2001-03-01), Tanaka et al.
patent: 08-279295 (1996-10-01), None
patent: 08279295 (1996-10-01), None

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