One-chip image processing apparatus

Details One-chip image processing apparatus One-chip image processing apparatus

2003-07-21

2004-10-26

Nguyen, Cuong (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S777000, C345S505000, C345S601000

Reexamination Certificate

active

06809422

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2003-066763, filed Mar. 12, 2003, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an image processing apparatus, particularly to a one-chip image processor. Further, the present invention relates to an image processing apparatus for use in, for example, computer graphics, computer vision, image filters, and the like.
2. Description of the Related Art
Generally, an image processing apparatus has an image processing section configured with a rasterizing section for preparing an address and a computing parameter, and a computing section for performing processing in units of pixels.
Conventionally, a processor used for computer graphics requires a highly functional rasterizing section for expanding an arbitrary triangle into pixels. Further, when high-level shading processing is performed for pixels, a complex computing section having a pipeline structure or a pixel pipeline is required. An image pipeline system is described in, for example, U.S. Pat. No. 6,198,488 of Lindholm et al. In such an image pipeline system, many circuits which do not require to operate when simple image processing is performed are included and latency until a processing result is output also becomes longer, which deteriorates processing efficiency.
On the other hand, a conventional image processor for use in computer graphics, image filters, or the like is configured with address-generating and computing sections having remarkably simple configurations. Therefore, when complex graphics processing is performed, data is frequently written into/read from a memory, which deteriorates processing efficiency.
Further, because a general versatile processor cannot utilize the parallelism of pixel processing unique to general image processing, processing efficiency is worse as compared with an image-processing-exclusive processor.
FIG. 1
shows one configuration example of a conventional image processing section. This image processing section uses a Digital Differential Analyzer (DDA) as a processing algorithm.
In the image processing section, a setup section
201
, a DDA section
202
, an expansion section
203
, a plurality of pixel processing sections
204
, a memory controller
205
, and an internal memory
206
are formed on the same semiconductor chip.
The setup section
201
, the DDA section
202
, and the expand section
203
perform rasterizing processing. The pixel processing sections
204
are directed for performing pixel processing, and each pixel processing section
204
includes a computing section
207
.
FIG. 2
shows one operation example of the pixel processing section
204
in FIG.
1
.
This example shows a case where eight pixel processing sections
204
are provided, and a stamp of 4×2 pixels is simultaneously processed by a pipe line of 4×2.
In the pixel processing section
204
in
FIG. 1
, when the computing section
207
performs loop computation processing a plurality of times, a plurality of neighboring pixels are processed by a different loop configured in the path from the setup section
201
to the computing section
207
, which makes control by the memory controller
205
complex.
U.S. Pat. No. 6,333,744 of Kirk et al discloses a graphics processing apparatus for performing processing with respect to pixels. The apparatus disclosed performs pixel processing at a texture stage and at a register combiner stage. Required data is read from a memory into the texture stage, where processing appropriate for graphics is performed. A color of a pixel is calculated using the data at the register combiner stage. At the register combiner stage, input data and a computation type are defined to the respective cascade-connected computing devices and data streams are flowed so that the pixels are processed. Therefore, the numbers of computing devices and items of input data are increased so that an input data designation method or a connection relationship between the computing devices is made more flexible.
As described above, with respect to the conventional image processing apparatus, there has not been proposed architecture of an image processor capable of efficiently performing image processing in computer graphics, computer vision, or image filtering, and the problem is desired to be eliminated.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided an image processing apparatus comprises a block expansion section formed in a semiconductor chip, which handles an area to be drawn in units of blocks each composed of a plurality of pixels and performs expansion calculation of information on a representative point of each block; and a plurality of pixel processing sections formed in the semiconductor chip, each of the plurality of pixel processing sections comprises: a pixel expanding section which receives block representative point information calculated in the block expanding section and expands information in units of pixels at least in a rectangular area from the information; and a computing section which receives information expanded by the pixel expanding section and performs computation in units of pixels from the information each of the plurality of pixel processing sections
9
, performs graphics processing in cooperation with the block expanding section, and performs image processing independent of the block expanding section.


REFERENCES:
patent: 6198488 (2001-03-01), Lindholm et al.
patent: 6333744 (2001-12-01), Kirk et al.
patent: 6388671 (2002-05-01), Yoshizawa et al.
patent: 6642930 (2003-11-01), Matsuura et al.

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