One-chip first-in first-out memory device having matched write a

Details One-chip first-in first-out memory device having matched write a One-chip first-in first-out memory device having matched write a

1991-08-19

1993-06-15

Fears, Terrell W.

Static information storage and retrieval

Read/write circuit

365 78, 36518904, G11C 1300

Patent

active

052205290

ABSTRACT:
A write operation is performed by using a sequentially-incremented write address upon a first-in first-out memory device, and a read operation is performed by using a sequentially-incremented read address upon the first-in first-out memory device. The write address is cleared by a write reset signal, and the read address is cleared by a read reset signal. A delay circuit is provided to coincide an effective timing of the write reset signal in the memory cell array with that of the read reset signal in the memory cell array.

REFERENCES:
patent: 48660255 (1989-08-01), Shimohigashi et al.
Texas Instruments Catalog: 1M Bit Field Memory TMS4C1050, May, 1987, pp. 2-37-2-48.

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