One-chip clock synchronized memory device

Details One-chip clock synchronized memory device One-chip clock synchronized memory device

1998-02-04

1999-10-19

Heckler, Thomas M.

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

711170, G06F 1200

Patent

active

059681810

ABSTRACT:
A one-chip clock synchronized memory device comprises a memory constituted by an ordinary data storage area and a sequence storage area. The sequence storage area sequentially stores logic sequence data including control signals, data signals and address signals. A data area control circuit controls reading and writing of data to and from the ordinary data storage area. Logic sequence data storage means receives logic sequence data and writes the received data to the sequence storage area. The memory device is characterized by its ability to accommodate input data sequentially as logic sequence data while performing ordinary data storage operations.

REFERENCES:
patent: 4949244 (1990-08-01), Kubo et al.
patent: 5317714 (1994-05-01), Nakagawa et al.
patent: 5727232 (1998-03-01), Iida et al.

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