One-bit memory cell in static random access memory device with P

Details One-bit memory cell in static random access memory device with P One-bit memory cell in static random access memory device with P

1992-11-30

1995-04-04

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Non-single crystal, or recrystallized, semiconductor...

Field effect device in non-single crystal, or...

257 69, 257369, 257903, H01L 2711, H01L 2978

Patent

active

054040302

ABSTRACT:
An improved static random access memory device of the CMOS load memory cell type for storing one-bit information is capable of 4M bit or greater memory capacity. Each memory cell includes two transfer transistors, two driving transistors, and two load transistor elements. Each load transistor element is a PMOS thin film transistor and comprises a source formed of first and second conductive layers and connected to a constant power source line, and a drain also formed of the first and second conductive layers and connected to the drain of a corresponding one of the driving transistors. A channel region of each load transistor element is composed only along the region defined by the second conductive layer and a respective gate is formed of a third conductive layer which is separated from the channel region by a gate insulating layer.

REFERENCES:
patent: 3673471 (1972-06-01), Klein et al.
patent: 4980732 (1990-12-01), Okazawa
patent: 5132771 (1992-06-01), Yamanaka et al.
patent: 5159416 (1992-10-01), Kudoh
patent: 5172203 (1992-12-01), Hayashi et al.
Furuta et al., "Hot-Carrier Induced Ion/Ioff Improvement of Offset PMOS TFT", NEC Corporation, pp. 27 and 28.
Uemoto et al., "A High-Performance Stacked-CMOS SRAM Cell by Solid Phase Growth Technique", 1990 Symposium on VLSI Technology, 1990 IEEE, pp. 21 and 22.
Ikeda et al., "A Polysilicon Transistor Technology for Large Capacity SRAMs", 1990 IEEE, pp. 18. 1.1-18. 1.4.

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