On-wafer burn-in of semiconductor devices using thermal...

Details On-wafer burn-in of semiconductor devices using thermal... On-wafer burn-in of semiconductor devices using thermal...

2002-06-27

2004-01-13

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C438S014000

Reexamination Certificate

active

06677172

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor device processing technology, and in particular, to a method for burning-in semiconductor devices that enables greatly reduced burn-in time and substantial energy cost savings.
DESCRIPTION OF THE RELATED ART
Semiconductor fabrication typically involves numerous process steps. Defects or other imperfections may be introduced to a chip at any of these process steps. If they remain undetected, such defects and imperfections are likely to result in the failure of the affected chip. To avoid chip failures due to such manufacturing defects or imperfections during the operating life of a chip, semiconductor manufactures rigorously test their finished chips before shipment to weed out any chips that are likely to fail as a result of manufacturing defects and imperfections that occur during the fabrication process.
“Burn-in” is a commonly-used procedure in semiconductor fabrication for stress testing semiconductor chips. The burn-in process allows the chip manufacturer to screen out defective chips as well as stabilizes the performance of the serviceable chips over their lifetime. The burn-in process generally involves operating the chips at elevated currents (e.g., about 2 to 5 times higher than the normal operating current) and temperatures (e.g., at ambient temperatures of about 50 to 100° C. higher than normal operating condition) for extended periods (e.g., up to 72 hours). During the burn-in process, chips prone to early failure are identified and eliminated. As such, the burn-in process greatly minimizes the problem of “infant mortality” in semiconductor devices. Moreover, it is known in the art that the operating parameters of semiconductor devices may shift during the early stage of its serviceable life. By burning-in the devices before shipment, so that any shifts in the chips' operating parameters occur by the end of the burn-in process, the chip manufacturer can deliver devices with stable and reliable performance to its customers.
Generally, when all process steps have been performed on a semiconductor wafer, the processed wafer is cut into individual dies. Each die is then encapsulated in a package typically made of metal, plastic or ceramic to produce a finished integrated circuit (IC) device or chip. Traditionally, burn-in is performed individually on each packaged device at this point in the manufacturing cycle. This approach is time-consuming because the burn-in process is performed chip-by-chip in serial fashion. It is also costly because a chip is not tested—and thus any defect is not detected—until the chip has been packaged. As such, costs for chip packaging material as well as for the packaging process are wasted on defective chips that must be discarded. In optoelectronic devices such as VCSEL (vertical cavity surface emitting laser) devices, it is common that the chip itself costs approximately 10 to 20 percent of the total raw material costs. This means that the costs for the packaging material (e.g., optical elements, TO (transistor outline) cans, etc.) and packaging process account for 80 to 90 percent of the entire packaged VCSEL device. Thus, it is highly desirable to have a mechanism whereby the chips are tested, and defective chips are rejected, before they are packaged such that costs for packaging raw material and packaging process are not unnecessarily incurred.
In light of the shortcomings of burning-in individual packaged devices, there have been recent efforts to perform the burn-in process on-wafer, i.e., before the processed semiconductor wafer is cut into individual dies. On-wafer burn-in allows the manufacturer to avoid the costs of packaging defective dies because they are identified and discarded before the packaging process begins. Currently, there are several approaches for conducting on-wafer burn-in. These different approaches are briefly discussed immediately below.
Some manufacturers use a “sacrificial wafer” approach to perform on-wafer burn-in. See, e.g., Wilburn L. Ivy, Prasad Godvarti, et al., “Sacrificial Metal Wafer Level Burn-In KGD”, 50
th
Electronic Components & Technology Conference, Paper S15P2, May 2000. In this approach, a sacrificial wafer, which is fitted with microscopic metal contacts for all of its dies, is placed on top of a target wafer so that the corresponding dies on the two wafers are properly aligned. The burn-in process is then performed on both wafers simultaneously by applying the appropriate elevated current to the sacrificial wafer from a current source. Although the dies on the target wafer have no metal contacts of their own for direct coupling to the current source, these dies on the target wafer receive the elevated current by way of the metal contacts of the dies on the sacrificial wafer. At the end of the burn-in process, both the sacrificial wafer and the target wafer are burnt-in as intended. The sacrificial wafer is removed from the target wafer, which can then be cut into individual dies and packaged for delivery.
Another approach to on-wafer burn-in makes use of a so-called “microprobe wafer.” See, e.g., D. L. Smith, D. K. Fork, R. L. Thornton, A. S. Alimonda, C. L. Chua, C. Dunnrowicz, and J. Ho, “Flip-Chip Bonding on 6-&mgr;m Pitch Using Thin-Film Microspring Technology”, Proceedings of the 48
th
Electronics Components & Technology Conference, Seattle, Wash., May 1998, pp. 325-329. This wafer comprises two metal films of different strengths such that micro-tips are formed at proper locations on the wafer surface when one of the films is lifted out due to the strength differential. The resulting wafer with these micro-tips can then be placed on top of a target wafer and used as an array of microprobes for burn-in purposes, in a fashion similarly to that described above with respect to the sacrificial wafer approach. This microprobe wafer approach is particularly suited for burning-in high density wafers where precise electrical contacts with each and every individual device on the wafer is relatively more difficult to achieve using conventional approaches.
Yet another approach to on-wafer burn-in involves the use of a “conducting fabric.” A fabric with well-controlled pH is placed on top of the target wafer to ensure that proper electrical contact is established for each die on the wafer so that burn-in of all dies can be accomplished. Still another approach involves using an elaborate probe card designed especially for the purposes of performing burn-in. See, e.g., Dennis R. Conti and Jody Van Horn, “Wafer Level Burn-In”, 50
th
Electronic Components & Technology Conference, Paper S21P4, May 2000. The probe card comprises numerous probes for contacting all devices on a wafer. The card is placed in contact with the target wafer to allow all devices on the wafer to be burnt-in in a single burn-in cycle. In most cases, such probe cards are expensive to manufacture and a particular probe card may be useful for only a limited number of wafers as dictated by the device layout. A further approach is to temporarily wire all of the devices on the wafer (in series or in parallel) to form a complete circuit (e.g., by way of a bus line). See, e.g., Conti and Van Horn, ibid. As such, the interconnected devices on the wafer can all be burnt-in by applying a burn-in current to a small number of contacts (e.g., two contacts). When the burn-in is completed, the wafer is diced into individual dies and in the process the temporary interconnections between dies are severed.
There is a significant commonality among all of the above-described on-wafer burn-in approaches: they all involve burning-in each and every device on a given wafer at the same time during one burn-in cycle. Unfortunately, these approaches require that a large burn-in current be maintained for the entire duration of the burn-in process. This translates to a significant level of power consumption for an extended period of time. As an example, in the fabrication of VCSEL devices, a typical 3-inch wafer can include 25,000 individual devices. Assuming a typical burn-in cur

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