On- the-fly partitionable computer bus for enhanced operation wi

Details On- the-fly partitionable computer bus for enhanced operation wi On- the-fly partitionable computer bus for enhanced operation wi

1997-08-13

1999-09-28

Ray, Gopal C.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710131, G06F 1300, G06F 1340, H04Q 352

Patent

active

059580330

ABSTRACT:
Method and apparatus for controlling a computer bus having first and second bus slots and operable with a bus controller at first and second data transfer rates. When the computer bus is operating at the first data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled to the address/data pins of both of the first and second bus slots, and the control pins of the bus controller are coupled only to the control pins of the second bus slot. When the computer bus is operating at the second data transfer rate, the bus is partitioned so that the address/data pins of the bus controller are coupled only to the address/data pins of the first bus slot, and the control pins of the bus controller are coupled only to the control pins of the first bus slot. The second data transfer rate may be faster than the first data transfer rate.

REFERENCES:
patent: 4535448 (1985-08-01), Baxter et al.
patent: 4922409 (1990-05-01), Schoellkopf et al.
patent: 5487155 (1996-01-01), Drewry et al.
patent: 5491814 (1996-02-01), Yee et al.
patent: 5572685 (1996-11-01), Fisher et al.
patent: 5751976 (1998-05-01), Okazawa et al.
patent: 5802355 (1998-09-01), Arroyo et al.

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