On-the-fly data integrity transfer system handling mixed block s

Details On-the-fly data integrity transfer system handling mixed block s On-the-fly data integrity transfer system handling mixed block s

1994-06-07

2000-10-10

Moise, Emmanuel L.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

714 48, 714800, 714804, 714819, 34082516, H03M 1300, G06F 1100

Patent

active

061311766

ABSTRACT:
An on-the-fly integrity checking system which dupicates data passing through a main systems bus, functions concurrently to recognize the size of data blocks being transferred from a sending module to a receiving module. Each word transferred is immediately parity checked. A counter indicates when the entire data block has transferred so as to initiate the comparison of an original block EDC signature with that of a internally generated EDC value to indicate the validity or invalidity of the data transfer. No delay is involved on the data transfer operations of the main system bus due to the integrity checking system operating independently as an independent module which does not delay data transfers on the main system bus.

REFERENCES:
patent: 4789986 (1988-12-01), Koizumi
patent: 4864531 (1989-09-01), Quatse
patent: 4866666 (1989-09-01), Francisco
patent: 5182752 (1993-01-01), DeRoo et al.
patent: 5243607 (1993-09-01), Tsang et al.
patent: 5285456 (1994-02-01), Cheney et al.
patent: 5313627 (1994-05-01), Amini et al.
patent: 5319752 (1994-06-01), Petersen et al.

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