On die termination device and semiconductor memory device...

Details On die termination device and semiconductor memory device... On die termination device and semiconductor memory device...

2008-07-29

2010-11-02

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S021000, C327S108000

Reexamination Certificate

active

07825683

ABSTRACT:
On die termination (ODT) device that can reduce the number of lines for transferring calibration codes to reduce the size of a chip including the ODT device. The ODT device includes a calibration circuit configured to generate calibration codes for determining a termination resistance, a counting circuit configured to generate counting codes increasing with time. A transferring circuit of the device is configured sequentially to transfer the calibration codes in response to the counting codes. A receiving circuit is configured sequentially to receive the calibration codes from the transferring circuit in response to the counting codes. A termination resistance circuit of the device is configured to perform impedance matching using a resistance determined according to the calibration codes.

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patent: 7528626 (2009-05-01), Kim
patent: 2008/0054936 (2008-03-01), Fujisawa
patent: 2008/0054937 (2008-03-01), Kinoshita et al.
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patent: 2009/0009213 (2009-01-01), Osanai et al.
patent: 1020040021110 (2004-03-01), None
patent: 1020040083814 (2004-10-01), None

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