Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2006-12-28
2008-11-25
Cho, James H (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S093000
Reexamination Certificate
active
07456651
ABSTRACT:
An on-die termination apparatus for a semiconductor memory according to the invention includes: a first D/A converting unit that outputs a first voltage corresponding to a first code; a first comparing unit that compares the first voltage to a reference voltage and corrects comparison results between the first voltage and the reference voltage, to output first comparison signals, wherein the first comparing unit is operated after a lapse of time from an initial operation time of the first D/A converting unit; a first counter that counts up or down the first code to correspond to the first comparison signals; a second D/A converting unit that outputs a second voltage corresponding to a second code; a second comparing unit that compares the second voltage to the reference voltage and corrects comparison results between the second voltage and the reference voltage, to output seconds comparison signals, wherein the second comparing unit is operated after a lapse of time from an initial operation time of the second D/A converting unit; a second counter that counts up or down the second code to correspond to the second comparison signals; and a timing control unit that controls timings when the first D/A converting unit, the first comparing unit, the first counter, the second D/A converting unit, the second comparing unit, and the second counter start to operate.
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Cho James H
Hynix / Semiconductor Inc.
Kaminski Jeffri A.
Venable LLP
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