Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-05-13
2008-05-13
Cho, James H. (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S016000
Reexamination Certificate
active
07372294
ABSTRACT:
An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding unit for decoding an inputted address to output a plurality of decoding signals to set a termination impedance; an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.
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Korean Office Action issued in corresponding Korean Patent Application No. KR. 2005-0117640, dated Oct. 31, 2006.
Cho James H.
Hynix / Semiconductor Inc.
McDermott Will & Emery LLP
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