Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2006-05-30
2006-05-30
Tu, Christine T. (Department: 2138)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S724000, C714S819000
Reexamination Certificate
active
07055060
ABSTRACT:
A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.
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Honcharik Alexander J.
Jamil Sujat
Nguyen Hang T.
Tu Steven J.
Blakely , Sokoloff, Taylor & Zafman LLP
Intel Corporation
Tu Christine T.
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