Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
1999-09-30
2001-12-04
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000, C326S087000, C326S027000
Reexamination Certificate
active
06326802
ABSTRACT:
FIELD
The invention relates to on-die adaptive arrangements for continuous process, voltage and temperature (PVT) compensation for termination impedances.
BACKGROUND
In the world of electrical signal transmission, it is known that if a traveling signal experiences any discontinuity (e.g., change in impedance) along a transmission path, such signal can experience undesirous effects such as signal reflection. More particularly, referencing
FIG. 1
for background discussion, shown is a first integrated circuit (IC) numbered IC
A
, a second IC numbered IC
B
, and a plurality of transmission lines IL
N−1
, IL
N
, IL
N+1
connected to input/output terminals and providing signal transmission paths therebetween, with the illustration of “•••” within such FIG. being indicative that there may be many more (e.g., hundreds of) input terminals and transmission lines interconnected therebetween. The transmission lines IL
N−1
, IL
N
, IL
N+1
will have a characteristic impedance, e.g., 50 ohms (&OHgr;). If IC
B
outputs a signal SIG from an input/output (I/O) terminal onto transmission line IL
N−1
, such signal SIG will travel along transmission line IL
N−1
, and unless an I/O terminal of IC
A
is impedance matched to the characteristic impedance of the transmission line IL
N−1
, such traveling signal will experience discontinuity and will experience undesirous effects such as a signal reflection REFL. Such reflection REFL is undesirous because it lessens a signal strength of the signal SIG which is actually inputted into IC
A
, and travels back to IC
B
. It may then reflect back from IC
B
if it is not matched to the transmission line impedance, and this reflection may interfere with subsequent signal reception at IC
A
.
As one method to avoid substantial impedance mismatch, an impedance such as an external resistor R
EXT
(
FIG. 1
) may be provided at each I/O terminal so as to impedance match the I/O terminal to the transmission line. With such impedance matching, little discontinuity and thus minimal reflections are experienced by a traveling signal at the end of the line. The problem with this approach is that typically a respective precision impedance (e.g., resistor) is needed for each I/O terminal, such precision impedances being relatively high in cost. Further, manufacturing costs, time and complexity are increased because the precision impedances must be connected to the respective I/O terminals. Still further, the external impedances take up valuable space (aka, real estate) on a printed circuit board (PCB), which is disadvantageous in the present trend of the computer industry to provide more and more dense and compacted apparatus (e.g., computers, servers, etc.).
While it would be nice to be able to provide precision resistors internally (i.e., on-die) within an IC, IC manufacturing processes vary substantially from manufacturing lot to manufacturing lot, and as a result of such manufacturing variations, IC components correspondingly vary making it very difficult and/or cost prohibitive to provide/guarantee such precision resistors. Further, even if such precision resistors could be provided on-die, such approach would still be disadvantageous in that use of precision resistors is a static technique which would not allow for adjustment at the time of IC installation to varying transmission lines, and which would not allow for continuous process, voltage and temperature compensations. That is, voltage and temperature environments, for example, within an IC and/or on signal transmission lines change over time during the operation of an apparatus, and accordingly, any matching arrangement should continuously be “adaptive” to such changes over time.
SUMMARY
The invention is directed to an impedance matching arrangement, including an adaptive circuit. The adaptive circuit includes a first adaptive portion allowing impedance matching according to a predetermined first weighting scheme, and a second adaptive portion allowing impedance matching according to a predetermined second weighting scheme which differs from the first weighting scheme.
REFERENCES:
patent: 5095231 (1992-03-01), Sartori et al.
patent: 5134311 (1992-07-01), Biber et al.
patent: 5559447 (1996-09-01), Rees
patent: 5677639 (1997-10-01), Masiewicz
patent: 5955894 (1999-09-01), Vishwanthaiah et al.
patent: 6114898 (2000-09-01), Okayasu
Jones Jeff R.
Lim Chee Bow
Newman Paul F.
Pasdast Gerald
Taylor Greg
Antonelli Terry Stout & Kraus LLP
Intel Corporation
Le Don Phu
Tokar Michael
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