Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-05-27
2002-04-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
06370676
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed to integrated circuit fabrication and test methodologies, and, in particular, to a method and apparatus for providing on-demand, performance sorting at tester, card, and system levels.
2. Discussion of the Prior Art
Sorting chips for a high performance category or low performance category is typically performed by using a continuously running ring oscillator at chip level testing. That is, the chips are typically tested at chip-level test, for example, by sensing and measuring the oscillator frequency. This requires the tester to set up the test program to monitor the oscillator frequency and the chips category must be printed on the module to insure its performance category. If the chip is assembled on a module, then there is no good way to categorize whether it is a fast chip or slow chip. Even if chip was to be sorted at module or system levels, sophisticated test equipment is required with longer test times necessary.
It would be highly desirable to provide a method and apparatus for providing performance sorting at a tester, card, and at a system level, on demand, in a simple and cost-effective manner.
SUMMARY OF THE INVENTION
The present invention is directed to an integrated circuit chip testing method and apparatus that provide performance sorting at a tester, at a card, and at a system level, on demand. According to the principles of the invention, there is provided a process sort test circuit for determining performance characteristic of an IC chip, the test circuit comprising: an input for receiving an input signal; a first path from the input to a first output for transmitting the input signal to the first output, the first path sensitive to variations in the manufacturing process for the IC chip (fast path); a second path from the input to a second output for transmitting the input signal to the second output, the second path being substantially less sensitive to the variations in the manufacturing process for the IC chip (slow path); and, a pulse generator coupled to the first and second outputs, the pulse generator including means for detecting a difference in arrival times of the input signal at the first and second outputs and for outputting a sort signal if the difference is of a preselected magnitude, wherein the sort signal enables output indication of a performance characteristic of the IC chip.
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Hayashi Masayuki
Keil Richard F.
Savaglio Robert J.
Chadurjian, Esq. Mark F.
International Business Machines - Corporation
Scully Scott Murphy & Presser
Speight Jibreel
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