Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-06-11
2001-11-27
Hayes, Gail (Department: 2131)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S719000, C714S735000
Reexamination Certificate
active
06324657
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to testing of integrated circuits, and more specifically to a method and apparatus that reduces the time and testing resources needed for testing of integrated circuits.
BACKGROUND OF THE INVENTION
Integrated circuits are extensively tested both during and after production, and, in some cases, routinely during use after they have been installed in products. For example, memory devices, such as random access memories (“RAMs”) and dynamic random access memories (“DRAMs”), are tested during production at the wafer level and after packaging, and they are also routinely tested each time a computer system using the DRAMs executes a power-up or “boot” routine when power is initially applied to the computer system. As the capacity of DRAMs and other memory devices continues to increase, the time required to test the DRAMs continues to increase, even though memory access times continue to decrease.
A typical RAM integrated circuit includes at least one array of memory cells arranged in rows and columns. Each memory cell must be tested to ensure that it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a “1”) are written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a “0”) are typically written to and read from the memory cells. A memory cell is determined to be defective when the data that is read from the memory cell does not equal the data that was written to the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern, e.g., 101010. . . , written to the memory cells in each row of the arrays.
One situation requiring testing of memory integrated circuits occurs during fabrication of integrated circuits. Fabrication yields are reduced when fabrication errors occur. Testing of integrated circuits during fabrication allows the sources of some fabrication errors to be promptly identified and corrected. Testing during fabrication may reduce costs by reducing the number of integrated circuits affected by a given fabrication error.
Another situation requiring testing of integrated circuits also occurs in fabrication of memory integrated circuits. Defective memory cells are identified by testing and are replaced with non-defective memory cells from a set of spare or redundant memory cells. In one conventional method for replacing defective memory cells, fuses on the integrated circuit are blown in a pattern corresponding to the pattern of defective memory cells to select rows or columns of redundant memory cells. The pattern is then read to replace the rows or columns that include the defective memory cells.
FIG. 1
is a simplified block diagram of several integrated circuits
10
and an automated tester
12
according to the prior art. Separate buses
14
are dedicated to couple each of the integrated circuits
10
to the automated tester
12
. The data buses
14
convey stimuli, known as background data, from the automated tester
12
to function circuits
16
, such as memory arrays, contained in the integrated circuits
10
that are being tested. Each function circuit
16
generates a response, such as read data, from the background data that are sent to that function circuit
16
. The data buses
14
also convey the read data from each function circuit
16
back to the automated tester
12
. The automated tester
12
compares the read data from each integrated circuit
10
that is being tested to a corresponding set of expect data. The expect data correspond to read data that would be provided by the integrated circuit
10
if its function circuit
16
was operating properly. When the read data and the corresponding expect data match, the integrated circuit
10
is considered to be functioning normally. When the read data do not match the corresponding expect data, the integrated circuit
10
that provided the read data is considered to be malfunctioning.
Each bus
14
can only convey data unambiguously from one integrated circuit
10
at a time to the automated tester
12
. In turn, the automated tester
12
can only accommodate a finite number of buses
14
, limiting the number of integrated circuits
10
that may be tested at one time. The number of memory integrated circuits
10
that may be coupled to the automated tester
12
at one time is known as the “fanout” for the automated tester
12
.
There is a need for an on-chip test circuit to test function circuits in a group of integrated circuits without requiring a separate module or control integrated circuit to read output signals from the function circuits in order to compare the output signals with expected output signals.
SUMMARY OF THE INVENTION
An on-chip test circuit is included in an integrated circuit for testing function circuits in the integrated circuit and for storing failure data from the tests. The on-chip test circuit includes an expect data register and a comparison circuit having a first input coupled to an output of the function circuits and a second input coupled to an output of the expect data register. The on-chip test circuit also includes a fail data register having an input coupled to an output of the comparison circuit. The fail data register stores data describing memory array failures. The combination of the comparison circuit and the fail data register allows many integrated circuits to be tested at one time without waiting for the each integrated circuit to provide read data to a tester and without bus contention. Testing of integrated circuits is thereby facilitated, reducing the time required for testing the integrated circuits and increasing the practical fanout from automated testers.
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patent: 5568437 (1996-10-01), Jamal
patent: 5659549 (1997-08-01), Oh et al.
patent: 5673270 (1997-09-01), Tsujimoto
patent: 5689466 (1997-11-01), Qureshi
patent: 5757815 (1998-05-01), Simogama et al.
patent: 5982681 (1999-11-01), Schwarz
patent: 6019502 (2000-02-01), Baeg et al.
patent: 6032274 (2000-02-01), Manning
patent: 0356999A2 (1990-03-01), None
Fister Wallace E.
Schoenfeld Aaron
Dorsey & Whitney LLP
Hayes Gail
Micro)n Technology, Inc.
Revak Christopher A.
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