On-chip word line voltage generation for DRAM embedded in logic

Details On-chip word line voltage generation for DRAM embedded in logic On-chip word line voltage generation for DRAM embedded in logic

1999-06-14

2000-11-14

Nelms, David

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

36523006, G11C 1604

Patent

active

061479144

ABSTRACT:
A memory system that includes a dynamic random access memory (DRAM) cell, a word line, and a CMOS word line driver fabricated using a conventional logic process. The word line driver is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell. A positive boosted voltage generator is provided to generate the positive boosted voltage, such that this voltage is greater than V.sub.dd but less than V.sub.dd plus the absolute value of a transistor threshold voltage V.sub.t. Similarly, a negative boosted voltage generator is provided to generate a negative boosted voltage, such that this voltage is less than V.sub.SS by an amount less than V.sub.t. A coupling circuit is provided between the word line driver and one of the positive or negative boosted voltage generators. The coupling circuit couples the word line driver to the selected one of the positive or negative boosted word line generators only when the word line is activated. The positive boosted voltage generator includes a charge pump control circuit that limits the positive boosted voltage to a voltage less than V.sub.dd plus V.sub.t. Similarly, the negative boosted voltage generator includes a charge pump control circuit that limits the negative boosted voltage to a voltage greater than V.sub.SS minus V.sub.t.

REFERENCES:
patent: 5297104 (1994-03-01), Nakashima
patent: 5371705 (1994-12-01), Nakayama et al.
patent: 5703827 (1997-12-01), Leung et al.
patent: 5986947 (1999-11-01), Choi et al.
patent: 6009023 (1999-12-01), Lu et al.

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