On chip voltage generation for low power integrated circuits

Details On chip voltage generation for low power integrated circuits On chip voltage generation for low power integrated circuits

1998-03-04

1999-12-14

Dinh, Son T.

Static information storage and retrieval

Powering

36518909, 36523006, G11C 700

Patent

active

060026308

DESCRIPTION:

BRIEF SUMMARY
BACKGROUND OF THE INVENTION

1. Field of the Invention
The present invention relates to on chip voltage generation techniques for producing a voltage on chip which is outside the range of a power supply voltage supplied to the chip; and more particularly to the generation of word line voltages on low power memory devices like flash memory, where the power supply voltage may be less than the read potential required for sensing data in the memory.
2. Description of Related Art
Integrated circuits have in the past been manufactured in order to work with a power supply voltage of about 5 volts, within a specified range of +/-10%. Of course other power supply voltages have been utilized. There is a current trend for many applications to design integrated circuits to work with lower power supply voltages. Lower voltages generally result in lower power operation for the devices, and are easier to supply using batteries in small devices. For example, one low supply voltage which is emerging as a standard is specified to operate over a range of about 2.7 to 3.6 volts. Other standards are being developed around even lower voltages.
On chip circuits however are often designed to operate at higher voltages for some purposes. For example, in memory devices, such as flash memory, word lines which supply a gate potential to memory cells are often designed to operate at a read potential of 4 volts or more. Thus, the low power supply voltage is insufficient to supply directly an on chip voltage high enough to drive the word lines. This problem is dealt with by including charge pumps or other voltage supply boosters on the integrated circuits in order to supply the higher working voltages on chip. See for example U.S. Pat. No. 5,511,026 entitled BOOSTED AND REGULATED GATE POWER SUPPLY WITH REFERENCE TRACKING FOR MULTI-DENSITY AND LOW VOLTAGE SUPPLY MEMORIES. The '026 patent describes an integrated circuit memory having charge pumps configured to supply word line voltages at a level higher than the supply potential. Furthermore, the '026 patent describes the use of on chip charge pumps to provide a plurality of word line voltages for multi-level/memory devices, so that a greater working margin is provided between the memory cell states, than would be normally available using a standard supply potential.
One problem associated with the prior art approaches to on chip charge pumps for these purposes arises from the nature of the supply potential to vary over a significant range. For example, when the supply potential ranges from about 2.7 to about 3.6 volts, the amount of voltage boost necessary to produce an on chip 4 volt potential varies from 1.3 to 0.4 volts. A single boost circuit to handle both extremes of the specified range of the supply potential with a 0.2 volt safety margin would require a 1.5 volt boost. The resulting output of the boost circuit would vary from about 4.2 volts when the supply potential is 2.7, to 5.1 volts when the supply potential is 3.6. Thus when the supply potential is at its high range, the power consumed by the boost circuit is wasted.
Furthermore, using traditional approaches, in which the pumping and boosting ratio is fixed, the on chip voltage is often boosted to a level that may be too high. For example, if the target level is specified at a range from 4.0 to 5.0 volts, the boost ratio for a supply potential ranging from 2.7 to 3.6 volts should be set at about 1.5 volts. However, such a ratio will cause the on chip voltage to reach approximately 5.1 volts when the supply potential is high. Even if a voltage regulator is utilized, a large fluctuation can occur on chip. When the on chip voltage is used for word lines on memory devices, such transient fluctuations can affect the sensing speed of sense amplifiers and decrease the reading speed, because the sense amplifiers cannot start to sense the output of the memory cells until the word line level is settled to the steady state.
Accordingly, it is desirable to provide a on chip voltage supply circuit for use with integrated circuits that p

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