On-chip variability impact simulation and analysis for...

Details On-chip variability impact simulation and analysis for... On-chip variability impact simulation and analysis for...

2007-09-18

2007-09-18

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

11147782

ABSTRACT:
An apparatus, method and system for performing a race analysis on an integrated circuit design which includes incorporating effects of on-chip transistor gate length (Lgate) and resistance variations into the race analysis and modeling on circuit performance while taking into account intra-chip transistor Lgate spatial variability.

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Orshansky, Michael; Milor, Linda; Chen, Pinhong; Keutzer, Kurt; Hu, Chenming “Impact of Spatial Intrachip Gate Length Variability on the Performance of High-Speed Digital Circuits” IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, vol. 21, No. 5, May 2002, (pp. 544-553).

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