On chip timing adjustment in multi-channel fast data transfer

Details On chip timing adjustment in multi-channel fast data transfer On chip timing adjustment in multi-channel fast data transfer

2006-01-24

2006-01-24

Thompson, A. M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C714S724000, C714S741000, C327S156000, C327S271000

Reexamination Certificate

active

06990644

ABSTRACT:
A method and structure for an apparatus for maintaining signal integrity between integrated circuits residing on a printed circuit board. The apparatus has adjustable delay circuitry within the circuits and the adjustable delay circuitry adjusts the timing of signals processed within the circuit. A phase monitor connects to the circuits. The phase monitor detects phase differences between signals output by the circuits. A controller connected to the delay circuitry, the phase monitor, and the controller adjust the delay circuitry to compensate for the phase differences.

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