On-chip testing of integrated circuits

Details On-chip testing of integrated circuits On-chip testing of integrated circuits

2002-09-24

2004-12-28

Garbowski, Leigh M. (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C714S030000, C714S733000

Reexamination Certificate

active

06836872

ABSTRACT:

BACKGROUND
This disclosure relates to on-chip testing of integrated circuits.
Built in self test (“BIST”) structures are design-for test (“DFT”) structures that may be included as part of an integrated circuit (“IC”). These on-chip structures allow for internal testing of IC components instead of more time-consuming external tests.
A BIST structure may be automatically incorporated during the design stage of an IC's development. When the chip is produced, the BIST structure allows for a relatively efficient means of detecting a fault in an IC component.


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Farshbaf, “Fault simulation for VHDL based test bench and BIST evaluation”, Nov. 19-21, 2001,Test Symposium, 2001. Proceedings. 10th Asian , pp.:396-401.

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