On-chip termination for a high-speed single-ended interface

Details On-chip termination for a high-speed single-ended interface On-chip termination for a high-speed single-ended interface

2007-04-17

2007-04-17

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S027000

Reexamination Certificate

active

10997447

ABSTRACT:
Circuits, methods, and apparatus that provide accurate on-chip termination impedances for high-speed data interface circuits. One embodiment of the present invention provides a series termination impedance for an output driver as well as shunt termination impedances for a receive circuit. These impedances are dynamically adjusted to match a ratio of an external precision resistor. Multiple coarse and fine-grain adjustments are automatically performed by the hardware. Adjustment may occur at power up or at programmable periodic intervals, and one or both of the impedances may be updated each time an interface begins to transmit or receive data. A specific embodiment utilizes a reference resistance that is made up of a parallel combination of resistors connected through MOS transistors. This resistance is adjusted by connecting or disconnecting the parallel resistors until it matches a ratio of an external resistor. The switch settings that provide a match are then used to adjust the termination impedances at the input and output pads.

REFERENCES:
patent: 6307791 (2001-10-01), Otsuka et al.
patent: 6424169 (2002-07-01), Partow et al.
patent: 6573746 (2003-06-01), Kim et al.

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