On-chip substrate bias generating circuit having substrate poten

Details On-chip substrate bias generating circuit having substrate poten On-chip substrate bias generating circuit having substrate poten

1988-05-11

1989-12-26

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307304, H03K 3354, H01L 1900, H01L 2704

Patent

active

048900117

ABSTRACT:
A semiconductor integrated circuit having a power supply terminal, ground terminal and a substrate bias terminal comprises a substrate voltage generating circuit connected to the power supply terminal and the ground terminal for generating a substrate bias voltage of a predetermined value and for applying the same to the substrate bias terminal, a MOS transistor provided between the substrate bias terminal and the ground terminal for bringing the substrate potential to the ground potential when the supply voltage of the power supply terminal exceeds a prescribed voltage value and a plurality of diode connected MOS transistors connected between the power supply terminal and the gate of the MOS transistor for deciding the prescribed voltage value.

REFERENCES:
patent: 3940747 (1976-02-01), Kuo et al.
patent: 4450515 (1984-05-01), Takemae et al.
patent: 4553047 (1985-11-01), Dillinger et al.
patent: 4695746 (1987-09-01), Tobita
patent: 4705966 (1987-11-01), Van Zanten
patent: 4733108 (1988-03-01), Truong
patent: 4739191 (1988-04-01), Puar
patent: 4794278 (1988-12-01), Vajdic
ISSCC 76: "A 70ns 1K MOS RAM" by R. D. Pashley et al., Session XII: Memory I, Feb. 19, 1976, pp. 138-139.
IEEE Trans. on Electron Dev.: "Single 5-V, 64K RAM with Scaled-Down MOS Structure", by H. Masuda et al., vol. ED-27, No. 8, Aug. 1980, pp. 1607-1612.
IEDM 85: "Static Transient Latch-Up Hardness in N-Well CMOS With On-Chip Substrate Bias Generator", by D. Takacs et al., 18.5, 1985, pp. 504-508.

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