On-chip series terminated CMOS(Bi-CMOS) driver

Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination

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326 33, H03K 1716

Patent

active

055326161

ABSTRACT:
A terminated driver circuit 10 having a controlled output impedance includes an external impedance 12 connected to a bias generator circuit 20 which is operable to generate a plurality of bias voltages in response to a reference current generated by bias generator circuit 20 wherein the reference current magnitude is a function of external impedance 12. An output driver circuit 30 is connected to bias generator circuit 20. Output driver circuit 30 has a plurality of output devices connected to a transmission line and is operable to receive the plurality of bias voltages from bias generator circuit 20 and multiplex them such that only a single bias voltage is driving a single output device at a time. The plurality of bias voltages causes the plurality of output devices to have specific, controlled impedances when conducting wherein the controlled output impedances match the characteristic impedance of a transmission line 40 being driven by terminated driver circuit 10 thereby reducing waveform reflections.

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patent: 4947061 (1990-08-01), Metz
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patent: 5095231 (1992-03-01), Sartori
patent: 5254883 (1993-10-01), Horowitz
patent: 5396028 (1995-03-01), Tomassetti

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