On-chip self-modification for PLDs

Details On-chip self-modification for PLDs On-chip self-modification for PLDs

2000-02-04

2001-07-03

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S039000, C326S040000

Reexamination Certificate

active

06255849

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to Programmable Logic Devices (PLDs). The invention particularly relates to a self-modification method for Field Programmable Gate Arrays (FPGAs) including Look-Up Table-based (LUT-based) logic elements.
BACKGROUND OF THE INVENTION
PLDs are general-purpose integrated circuits that typically include both user-configurable circuitry and configuration control circuitry. The configuration control circuitry typically includes a configuration memory array and addressing circuitry for writing configuration data, which is typically transmitted in a bit stream, into the configuration memory array. The user-configurable circuitry typically includes logic elements and associated interconnect resources that are connected to the memory cells of the configuration memory array, and are programmed (configured) by the configuration data stored in the configuration memory array to implement user-defined logic operations (that is, a user's circuit).
One characteristic that distinguishes early PLDs from more recent PLDs is the ability to partially reconfigure the configuration memory array. Early PLDs included relatively simple configuration control circuitry that only supported full configuration of the configuration memory array (i.e., each time a change in the configuration was needed, the entire configuration memory array was rewritten). In addition, the memory cells of the configuration memory array were only accessible through the configuration control circuitry in these early PLDs. More recent PLDs include relatively sophisticated configuration control circuitry that allows partial reconfiguration of selected portions of the configuration memory array. Further, in contrast to the early PLDs, some memory cells of the configuration memory circuit in these more recent PLDs can be rewritten with data transmitted over the interconnect resources of the user-configurable circuitry.
The above-mentioned differences and other differences between early and recent conventional PLDs are explained in additional detail in the following sections.
Early FPGAs
FIG.
1
(A) is a simplified diagram showing the user-configurable circuitry of an early FPGA
100
, which is a type of PLD. The configuration control circuitry of FPGA
100
is omitted from FIG.
1
(A) for clarity.
Referring to FIG.
1
(A), the user-configurable circuitry of FPGA
100
includes an array of configurable logic blocks (CLBs) CLB
1
,
1
through CLB
4
,
4
surrounded by input/output blocks (IOBs) IOB
1
through IOB
16
, and programmable interconnect resources that include vertical interconnect segments
120
and horizontal interconnect segments
121
extending between the rows and columns of CLBs and IOBs. Each CLB includes configurable combinational circuitry and optional output registers programmed to implement a portion of a user-defined logic operation. The interconnect segments of the programmable interconnect resources are configured using various switches to generate signal paths between the CLBs that link the logic function portions. Each IOB is similarly configured to selectively utilize an associated pin (not shown) of FPGA
100
either as a device input pin, a device output pin, or an input/output pin. The combinational circuitry of each CLB, the switches of the interconnect resources, and the configurable elements of the IOBs are all controlled by configuration data stored in configuration memory cells (not shown) that are controlled by the configuration control circuitry.
FIGS.
1
(B) through
1
(D) are simplified diagrams showing examples of the various switches associated with the programmable interconnect resources utilized in the user-configurable circuitry of FPGA
100
. As mentioned above, each switch is controlled by one or more configuration memory cells that store configuration data transmitted through the configuration control circuit (discussed above). FIG.
1
(B) shows an example of a six-way segment-to-segment switch
122
that selectively connects vertical wiring segments
120
(
1
) and
120
(
2
) and horizontal wiring segments
121
(
1
) and
121
(
2
) in accordance with configuration data stored in configuration memory cells M
1
through M
6
. Alternatively, if horizontal and vertical wiring segments
120
and
121
do not break at an intersection, a single transistor makes the connection. FIG.
1
(C) shows an example of a segment-to-CLB/IOB input switch
123
that selectively connects an input wire
110
(
1
) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with configuration data stored in configuration memory cells M
7
and M
8
. FIG.
1
(D) shows an example of a CLB/IOB-to-segment output switch
124
that selectively connects an output wire
115
(
1
) of a CLB (or IOB) to one or more interconnect wiring segments in accordance with configuration data stored in configuration memory cells M
9
through M
11
.
FIG.
1
(E) is a diagram showing simplified configuration control circuitry
130
of FPGA
100
. Configuration control circuitry
130
typically includes an array of configuration memory cells (M
0
,
0
through M
15
,
15
), and a control circuit for writing configuration data into the array of configuration memory cells. The array of configuration memory cells includes columns (frames) that are accessed by the control circuit, which includes a data shift register DSR and an address shift register ASR. To load configuration data into the configuration memory cells, an externally-generated bit stream including the configuration data is serially shifted into the data shift register DSR under control of a clocking mechanism until a frame of data is stored in data shift register DSR. This frame of data is then shifted in parallel into a column (frame) of configuration memory cells addressed by address shift register ASR. This process of serial shifting frames of configuration data from the bit stream and parallel shifting the frames into associated columns of configuration memory cells is repeated for all columns (frames) of the PLD.
FIG.
1
(F) is a simplified circuit diagram showing memory cell M
0
,
0
of the array of configuration memory cells shown in FIG.
1
(E). Memory cell M
0
,
0
includes a latch formed by inverters I
1
and I
2
that stores a bit value transmitted through a pass transistor T
1
. During configuration, when the token high bit is shifted into address shift register bit ASO (FIG.
1
(E)), the resulting high signal on line A
0
is applied to the gate of pass transistor T
1
, thereby allowing the configuration bit stored in data shift register bit position DSO to enter the latch via data line D
0
. The value stored in memory cell M
0
,
0
is then applied via output line Q and/or Q-bar (QB) to control a corresponding configurable logic block or configurable routing resource, such as the switching structures shown in FIGS.
1
(B) through
1
(D).
Advanced FPGAs
While early FPGAs (such as FPGA
100
, discussed above) provided significant advantages over other early PLD types, several features have been incorporated into advanced FPGAs that have provided further advantages. One such feature is the ability to program (reconfigure) at least some of the configuration memory cells through the interconnect resources, thereby allowing a user to modify the logic function performed by an advanced FPGA while the FPGA is operating. Another feature is the ability to reconfigure a portion of an advanced FPGA through the configuration control circuit. Yet another feature of some advanced FPGAs is the ability to perform full and partial reconfiguration via a standard JTAG (Boundary Scan) interface circuitry.
FIG.
2
(A) is a split-level perspective view showing a simplified representation of an advanced FPGA
200
, which is consistent with the Virtex™ family of FPGAs produced by Xilinx, Inc. of San Jose, Calif.
Similar to most integrated circuits, FPGA
200
includes programmable circuitry formed on a semiconductor substrate that is housed in a package having externally accessible pins. However, to simplify the following descri

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