On-chip power-ground inductance modeling using effective...

Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design

Reexamination Certificate

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C716S030000, C716S030000, C703S014000

Reexamination Certificate

active

06981230

ABSTRACT:
An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

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Gala, Kaushik, et al.,On-Chip Inductance Modeling and Analysis, Annual ACM IEEE Design Automation Conference, Proceedings of the 37thconference on Design Automation, 2000, pp. 63-68, ACM Press, New York, NY, USA, ISBN: 1-58113-187-9.

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