Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1997-08-29
2000-01-11
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375371, 375373, 375375, 375376, 375226, 375327, 327156, 327160, H03D 324, H04L 2536, H04L 2540, H04L 700
Patent
active
060144173
ABSTRACT:
A method and circuitry are provided for generating a phase shift in the recovered clock in a high speed, digital data recovery phase locked loop. Since phase step injection can be done in a closed loop environment, the dynamic of the real time phase step response of the PLL can be analyzed using a phase meter. In an open-loop environment, the output of the phase meter with a step response of 60 degree phase shift tracks closely with the internal RC response at the multi-phase outputs of the PLL's phase-to-frequency converter. Since the register and capacitor values vary with process, the scheme for verifying the relative accuracy of the PLL's internal filters can be verified without actually probing the device.
REFERENCES:
patent: 4376268 (1983-03-01), Moriya et al.
patent: 5056054 (1991-10-01), Wong et al.
patent: 5224125 (1993-06-01), Wong et al.
patent: 5351275 (1994-09-01), Wong et al.
patent: 5646967 (1997-07-01), Hee et al.
patent: 5651036 (1997-07-01), Hee et al.
patent: 5943379 (1999-08-01), Wong et al.
Hee Wong
Li Gabriel
Chin Stephen
Maddox Michael W.
National Semiconductor Corporation
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