On-chip memory redundancy circuitry for programmable non-volatil

Details On-chip memory redundancy circuitry for programmable non-volatil On-chip memory redundancy circuitry for programmable non-volatil

1996-02-05

1997-07-15

Yoo, Do Hyun

Static information storage and retrieval

Read/write circuit

Bad bit

36518509, 36518909, 365201, 3652335, 36523008, 365236, G11C 2900

Patent

active

056489340

ABSTRACT:
A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells. A system including a programming machine and the programmable non-volatile memory device, and methods for programming such memory devices, are also disclosed.

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Vancu, Radu et al., "Nonvolatile and Fast Static Memories", 1990 IEEE Intl. Solid State Cir. Conf., pp. 64-65.

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