On-chip memory map for processor cache macro

Details On-chip memory map for processor cache macro On-chip memory map for processor cache macro

1995-06-06

1998-06-02

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

711138, 711145, G06F 1208

Patent

active

057617198

ABSTRACT:
A computer processor architecture which employs an on-chip cache macro and an on-chip memory map is described. The memory map contains indicia of the cachability of different segments of off-chip memory, preferably along with an indication of the read/write status of each off-chip memory segment. A processor generated address signal is then compared on-chip with the memory map to ascertain whether the generated signal falls within a segment which is cachable or uncachable and which is read-only or read/write.

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