Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2002-01-11
2004-09-28
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S083000
Reexamination Certificate
active
06798237
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to on-chip impedance matching circuits, and more particularly, to on-chip impedance matching circuits that are sensitive to process, voltage, and temperature variations.
Prior art circuits have provided off-chip impedance matching circuits that reduce the e; reflection of signals on transmission lines. Off-chip impedance matching circuits typically include one or more off-chip resistors. The off-chip resistors are coupled to an input/output (I/O) pin of an integrated circuit to provide impedance matching.
Some integrated circuit have hundreds of I/O pins that require impedance matching circuitry. In these integrated circuits, a separate impedance matching resistor must be coupled to each of the I/O pins. Hundreds of impedance matching resistors must be coupled to such an integrated circuit to provide adequate impedance matching. Thus, prior art off-chip impedance matching circuits substantially increase the amount of board space required.
BRIEF SUMMARY OF THE INVENTION
The present invention provides integrated circuits with on-chip impedance matching techniques, which greatly reduce the number of off-chip resistors that are coupled to the integrated circuit. On-chip impedance matching circuits of the present invention are associated with a plurality of I/O pins on an integrated circuit. Circuitry of the present invention may include a resistor divider that has a resistor and an on-chip transistor. The resistance of the on-chip transistor and a voltage output signal of the resistor divider vary with process, temperature, and voltage of the integrated circuit. The effective channel W/L ratio of the impedance matching circuit changes in response to the voltage output signal of the resistor divider, so that changes in the impedance of the impedance matching circuit caused by the variations in process, temperature, and/or voltage are minimized.
REFERENCES:
patent: 4719369 (1988-01-01), Asano et al.
patent: 4954729 (1990-09-01), Urai
patent: 5111081 (1992-05-01), Atallah
patent: 5134311 (1992-07-01), Biber et al.
patent: 5164663 (1992-11-01), Alcorn
patent: 5179300 (1993-01-01), Rolandi et al.
patent: 5359235 (1994-10-01), Coyle et al.
patent: 5374861 (1994-12-01), Kubista
patent: 5592510 (1997-01-01), Van Brunt et al.
patent: 5602494 (1997-02-01), Sundstrom
patent: 5623216 (1997-04-01), Penza et al.
patent: 5726582 (1998-03-01), Hedberg
patent: 5726583 (1998-03-01), Kaplinsky
patent: 5764080 (1998-06-01), Huang et al.
patent: 5864715 (1999-01-01), Zani et al.
patent: 5939896 (1999-08-01), Hedberg
patent: 5955911 (1999-09-01), Drost et al.
patent: 5970255 (1999-10-01), Tran et al.
patent: 6008665 (1999-12-01), Kalb et al.
patent: 6026456 (2000-02-01), Ilkbahar
patent: 6037798 (2000-03-01), Hedberg
patent: 6049255 (2000-04-01), Hagberg et al.
patent: 6064224 (2000-05-01), Esch, Jr. et al.
patent: 6087847 (2000-07-01), Mooney et al.
patent: 6097208 (2000-08-01), Okajima et al.
patent: 6100713 (2000-08-01), Kalb et al.
patent: 6118310 (2000-09-01), Esch, Jr.
patent: 6147520 (2000-11-01), Kothandaraman et al.
patent: 6154060 (2000-11-01), Morriss
patent: 6157206 (2000-12-01), Taylor et al.
patent: 6181157 (2001-01-01), Fiedler
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6252419 (2001-06-01), Sung et al.
patent: 6329836 (2001-12-01), Drost et al.
patent: 6356106 (2002-03-01), Greeff et al.
patent: 6362644 (2002-03-01), Jeffery et al.
patent: 6366128 (2002-04-01), Ghia et al.
patent: 6411126 (2002-06-01), Tinsley et al.
patent: 6424169 (2002-07-01), Partow et al.
patent: 6445245 (2002-09-01), Schultz et al.
patent: 6448813 (2002-09-01), Garlepp et al.
patent: 6466063 (2002-10-01), Chen
patent: 6489837 (2002-12-01), Schultz et al.
Altera, Apex 20K “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Altera, Apex II “Programmable Logic Device Family,” Altera Corporation, Ver. 1.1, May 2001.
Esch and Manley, Theory and Design of CMOS HSTL I/O Pads, The Hewlett Packard Journal, Aug. 1998.
Xilinx, “Virtex-II 1.5V Field Programmable Gate Arrays,” Xilinx, DSO3102 (v1.5), Apr. 2, 2001.
Bendak, M. et al. (1996). “CMOS VLSI Implementation of Gigabyte/second computer network links,” Dept. of Electrical and Computer Engineering, University of California at San Diego, La Jolla, CA 92093-0407,IEEE International Symposium on Circuits and Systemspp. 269-272.
Boni, A. et al. (2001). “LVDS I/O Interface for Gb/s-per-Pin Operation in 0.35-um CMOS,” IEEE Journal of Solid-State Circuits, 36(4):706-711.
Nguyen Khai
Sung Chiakang
Wang Bonnie I.
Wang Xiaobao
Altera Corporation
Cahill Steven J.
Chang Daniel
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