On-chip ESD protection in dual voltage CMOS

Details On-chip ESD protection in dual voltage CMOS On-chip ESD protection in dual voltage CMOS

1999-03-30

2000-10-24

Monin, Jr., Donald L.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257500, 257546, 257392, H01L 2362

Patent

active

061371440

ABSTRACT:
In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

REFERENCES:
patent: 5276371 (1994-01-01), Jinbo
patent: 5374565 (1994-12-01), Hsue et al.
patent: 5438213 (1995-08-01), Tailliet
patent: 5455436 (1995-10-01), Cheng
patent: 5508548 (1996-04-01), Tailliet
patent: 5515226 (1996-05-01), Tailliet
patent: 5548134 (1996-08-01), Tailliet
patent: 5576570 (1996-11-01), Ohsawa et al.
patent: 5897348 (1999-04-01), Wu
patent: 5953606 (1999-09-01), Huang et al.
Duvvury, et al. "ESD: A Pervasive Reliability Concern for IC Technologies", Proceedings of the IEEE, vol. 81, No. 5, May 1993, pp. 690-702.

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