On chip error correction for devices in a solid state drive

Details On chip error correction for devices in a solid state drive On chip error correction for devices in a solid state drive

1995-10-31

2001-12-11

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C365S201000, C365S200000

Reexamination Certificate

active

06330688

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field Of The Invention
This invention relates to microprocessor controlled storage devices such as flash EEPROM memory arrays, and more particularly, to methods and apparatus for minimizing power consumption in such storage devices.
2. History of the Prior Art
Recently, storage devices such as flash electrically-erasable programmable read-only memory (EEPROM) arrays have been used as a new form of long term storage. A flash EEPROM memory array is constructed of a large plurality of floating-gate metal-oxide-silicon field effect transistor devices arranged as memory cells in typical row and column fashion with circuitry for accessing individual cells and placing the memory transistors of those cells in different memory conditions. Such memory transistors may be programmed by storing a charge on the floating gate. This charge remains when power is removed from the array. This charge (a “zero” or programmed condition) or its absence (a “one” or erased condition) may be detected when the device is read.
These arrays may be designed to provide a smaller lighter functional equivalent of an electromechanical hard disk drive which operates more rapidly and is not as sensitive to physical damage. Flash EEPROM memory arrays are especially useful in portable computers where space is at a premium and weight is extremely important. In order to allow flash EEPROM memory arrays to accomplish the storage functions normally accomplished by electromechanical hard disk drives, one type of flash memory manufactured by Intel Corporation of Santa Clara, Calif., utilizes on-chip control circuitry which is especially designed to respond to the commands and utilize the data furnished to accomplish the various read, write, and erase functions necessary to the storage and retrieval of data using a row and column array of flash devices. An advanced embodiment of this flash memory includes a microprocessor which exerts overall control of the functions of the storage array.
In general, a flash EEPROM memory array is divided into blocks of memory cells which are connected so that each entire block of memory cells may be erased simultaneously. Such an erasure places all of the devices in the block into the erased condition. Thereafter, a device may be individually programmed to store data.
Since all of the memory transistors of a block of the array are joined so that they may be erased together, a cell in a programmed condition cannot be switched to the erased state until the entire block of the array is erased. Thus, while an electro-mechanical hard disk drive typically stores information in a first area of the disk and then rewrites that same area of the disk when the information changes, this is not possible with a flash EEPROM memory array without erasing all of the valid information that remains in that block along with the invalid information. Consequently, in prior art arrangements, when the information at a data entry changes, the changed information is written to a new sector on a block of the array containing empty (erased) cells rather than written over the old data; and the old data is marked as invalid. Then, after a sufficient portion of a block has been marked invalid, the entire block is erased.
Because of this arrangement by which data is replaced, each block of the array will after some time have a number of invalid entries which cannot be used for storage. Consequently, the array fills with data as the data previously stored is changed; and a point will come when it is necessary to clear the invalid information from a block in order to provide space for new or changed information to be stored. When erasure of a block occurs, all of the remaining valid data stored in the block to be erased is written to a new block; the space from which the data was read is marked invalid; and then the entire invalid block is erased and put back into use as a clean block of memory. Consequently, there must be some number of blocks kept empty to accomplish the erase process.
Prior art forms of flash memories have provided error detection and correction arrangements. Because of this unique form of storage, if a hardware error occurs in a block of the array, it has been necessary to remove that block of the array from operation. Blocks of flash memory are relatively expensive compared to other forms of storage, so this is an undesirable characteristic. Moreover, since there are only a limited number of spare blocks of flash memory in an array, ultimately, this error correction approach limits the ability of the array to continue functioning.
It is desirable to provide a new form of error correction for flash EEPROM memory arrays which does not require the removal of blocks of flash memory from operation.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide an improved error correction arrangement for a flash EEPROM memory array.
This and other objects of the present invention are realized by an error correction arrangement for a flash EEPROM array including a plurality of blocks of row and column flash EEPROM devices, each of the blocks including a redundant array circuit, means for sensing when a hardware error has occurred in a block of the flash EEPROM array, and a circuit for replacing a bad array circuit with the redundant array circuit in response to detection of a hardware error.
These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.


REFERENCES:
patent: 5473753 (1995-12-01), Wells et al.
patent: 5490264 (1996-02-01), Wells et al.
patent: 5535328 (1996-07-01), Harari et al.
patent: 5544118 (1996-08-01), Harari
patent: 5691945 (1997-11-01), Liou et al.

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