Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-05-30
2003-12-09
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06662347
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to Integrated Circuits (ICs), and particularly but not exclusively to Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGAs) having on-chip diagnostic arrangements.
BACKGROUND OF THE INVENTION
In the field of this invention it is known for ASIC and FPGA designs to have an inbuilt diagnostic or debugging port which allows the monitoring of internal data buses, address buses and control signals. When a diagnostic test is being performed, the diagnostic port is typically coupled directly to an external logic analyser or oscilloscope and signals internal to the IC are multiplexed onto the port so that a trace can be obtained at the external device. During the bring-up and test phases of an IC's development, such traces are often invaluable in the analysis of a design problem as they can help to determine the internal state of the IC when that problem occurs.
However, this approach has the disadvantage that the number of signals that can be observed through a diagnostic port at any one time is limited. IC pin assignment priority is necessarily given to functional Input/Output signals and to power. The number of spare pins left over that can be assigned to a diagnostic port is therefore usually severely limited.
Traditional diagnostic methods were arranged to output an entire bus onto the diagnostic port for analysis. However, if the width of an internal bus exceeds that of the diagnostic port, then it is not possible to monitor the entire bus in a single test run. The internal bus must be divided into segments and several test runs must be performed with a different segment multiplexed onto the diagnostic port each time. For instance, to monitor a 128-bit internal data bus through a 32-bit diagnostic port, four separate runs are needed to trace the entire bus.
In addition to this, it is often useful if the trace of the bus is accompanied by a trace of the signals that control the bus. In order to make room for these control signals the size of the internal bus segment being monitored during a test run must be reduced. This results in an even greater number of test runs in order to obtain a complete trace of the internal bus and its control signals. All of the above considerations extend the time necessary for the bring-up phase of a new IC design.
A need therefore exists for an on-chip diagnostic system, integrated circuit and method wherein the abovementioned disadvantages may be alleviated.
STATEMENT OF INVENTION
In accordance with a first aspect of the present invention there is provided an on-chip diagnostic system for use with an internal bus of an integrated circuit, the bus having a number of data lanes, the system comprising: a register arranged to store a data pattern; a comparator arrangement coupled to receive data signals from each of the data lanes of the internal bus and further coupled to receive the data pattern from the register, for providing a compared output; and, a decoding arrangement coupled to receive the compared output, for providing a decoded integer output signal, wherein the decoded integer output signal identifies one of the number of data lanes in the case that the one of the number of data lanes contains data signals corresponding to the data pattern stored in the register.
In accordance with a second aspect of the present invention there is provided an integrated circuit comprising: an internal bus having a number of data lanes; a register arranged to store a data pattern; a comparator arrangement coupled to receive data signals from each of the data lanes of the internal bus and further coupled to receive the data pattern from the register, for providing a compared output; and, a decoding arrangement coupled to receive the compared output, for providing a decoded integer output signal, wherein the decoded integer output signal identifies one of the number of data lanes in the case that the one of the number of data lanes contains data signals corresponding to the data pattern stored in the register.
Preferably, there is provided an integrated circuit comprising at least two integrated circuits of the second aspect, wherein the at least two integrated circuits share a common register.
Preferably, there is provided the system or circuit of either aspect further comprising a diagnostic port coupled to receive the decoded integer output signal, and arranged to provide the decoded integer output signal to an external diagnostic device.
Preferably a diagnostic port is coupled to receive the decoded integer output signal, and arranged to provide the decoded integer output signal to an external diagnostic device. The comparator arrangement preferably has a number of comparators, the number of comparators being equal to the number of data lanes of the bus.
Preferably an output flag circuit is provided, which is arranged to provide an output flag in the case that the one of the number of data lanes contains data signals corresponding to the data pattern stored in the register. The output flag circuit is preferably an OR gate having a number of inputs coupled to receive the compared outputs from each of the number of comparators.
Each of the number of comparators preferably has an input width equal to the width of the data lanes. Preferably each data lane is a positive integer number of byte lanes, and the data pattern comprises the positive integer number of bytes. The integer number is preferably one, the data lane being a byte lane comprising 8 bits, and the data pattern being a byte pattern comprising 8 bits.
In this way the entire bus may be monitored in a single test run using the diagnostic port. In addition, a trace of bus control signals may be made at the same time. The number of test runs is therefore reduced and the time taken for the bring-up phase of a new IC design is considerably shortened.
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patent: 5717909 (1998-02-01), Nemirovsky et al.
patent: 5787007 (1998-07-01), Bauer
patent: 6430727 (2002-08-01), Warren
patent: 6477683 (2002-11-01), Killian et al.
Bluestone Randall J.
Dinh Paul
Harrington & Smith ,LLP
International Business Machines - Corporation
Smith Matthew
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