On-chip Delta-I noise clamping circuit

Details On-chip Delta-I noise clamping circuit On-chip Delta-I noise clamping circuit

1980-12-19

1983-08-09

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307200A, 307551, 365206, H03H 1146, H03H 512

Patent

active

043981062

ABSTRACT:
A clamping circuit to reduce self-induced switching noise in a multi-chip module semiconductor structure. A module section interconnects the chips and the chips have a power supply and power leads respectively. An impedance path is defined between each of the chips and the power supply to define a current path for switching noise through the top of the module. A high impedance path is defined for voltages below a predetermined upper limit of the chip supply voltage and a low impedance path is defined by the clamping circuit for the voltage range where noise superimposed on the chip supply voltage occurs.

REFERENCES:
patent: 3859638 (1975-01-01), Hume, Jr.
patent: 3936863 (1976-02-01), Olmstead
patent: 4027177 (1977-05-01), Davis
patent: 4095163 (1978-06-01), Montague
patent: 4220876 (1980-09-01), Ray
patent: 4323792 (1982-04-01), Bergmann et al.
M. Taub & D. Schilling, Digital Integrated Electronics, McGraw-Hill, 1977, pp. 241-243, and 306.
A. R. Berding, "Transistor with a Controlled Beta", IBM Tech. Disc. Bull.; vol. 10, #2; Jul. 1967, pp. 182-183.
A. Debrita, H. Geller, M. Yungfleisch, "Noise Suppression Circuit", IBM Tech. Disc. Bull.; vol. 15, #1; Jun. 1972, p. 259.
S. Wiedmann, "Low-Voltage Clipping Circuit", IBM Tech. Disc. Bull.; vol. 11, #10; Mar. 1969, p. 1367.

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