On-chip bus architecture that is both processor independent and

Details On-chip bus architecture that is both processor independent and On-chip bus architecture that is both processor independent and

1998-04-17

2000-09-19

Etienne, Ario

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710100, 710101, 710126, 710129, 710107, G06F 1300

Patent

active

061226904

ABSTRACT:
A bus in an integrated circuit uses bus interfaces to couple functional blocks to the bus in a processor independent and scalable manner. Various embodiments of the bus interfaces include a bus interface for a bus master functional block, a bus interface for a slave functional block, and a bus interface for either a bus master functional block or a slave functional block. Each bus interface includes a state machine that has at least two operational modes including a fast operational mode having two states and a normal operational mode having at least four states. A bus interface coupled to a bus master functional block implements an operational mode and a bus interface coupled to a slave functional block operates in a complementary operational mode. Each bus interface is also equipped to facilitate scaling of the address and/or data width on the bus. Various embodiments of the bus interfaces are also equipped to support multiple bus masters, broadcast writes, burst mode transfers, and/or tri-states on the bus.

REFERENCES:
patent: 5678009 (1997-10-01), Bains et al.
patent: 5727171 (1998-03-01), Iachetta, Jr.
patent: 5740115 (1998-04-01), Ishibashi et al.
patent: 5768628 (1998-06-01), Priem
patent: 5911052 (1999-06-01), Singhal et al.

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