Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2003-12-17
2008-03-04
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S306000, C710S308000
Reexamination Certificate
active
07340548
ABSTRACT:
This disclosure involves an on-chip bus architecture involving an on-chip bus that includes a collector node and at least one device node. Each device node is in communication with an on-chip device. The collector node is capable of conducting the multiple outstanding transactions with a plurality of on-chip devices over the on-chip bus wherein each on-chip device transmits all of its data signals across the on-chip bus in the form of packets. The on-chip bus includes at least one bus register, and each of the multiple on-chip devices includes at least one device register. The on-chip bus can provide top level register to register communications between the device register and the bus register. In one version, the on-chip bus is a distributed packet on-chip (DPO) bus.
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Dang Khanh
Microsoft Corporation
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