Offset spacer formation for strained channel CMOS transistor

Details Offset spacer formation for strained channel CMOS transistor Offset spacer formation for strained channel CMOS transistor

2008-01-22

2008-01-22

Landau, Matthew C. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S900000, C257SE29266

Reexamination Certificate

active

07321155

ABSTRACT:
A strained channel transistor and method for forming the same, the strained channel transistor including a semiconductor substrate; a gate dielectric overlying a channel region; a gate electrode overlying the gate dielectric; source drain extension (SDE) regions and source and drain (S/D) regions; wherein a stressed dielectric portion selected from the group consisting of a pair of stressed offset spacers disposed adjacent the gate electrode and a stressed dielectric layer disposed over the gate electrode including the S/D regions is disposed to exert a strain on a channel region.

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patent: 6797572 (2004-09-01), Jeon et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 6867433 (2005-03-01), Yeo et al.
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patent: 7001837 (2006-02-01), Ngo et al.
patent: 2003/0181005 (2003-09-01), Hachimine et al.
patent: 2004/0262784 (2004-12-01), Doris et al.

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