Offset-gate-type semiconductor device

Details Offset-gate-type semiconductor device Offset-gate-type semiconductor device

2001-12-13

2003-04-22

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S339000

Reexamination Certificate

active

06552389

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2000-380094, filed Dec. 14, 2000; and No. 2001-283974, filed Sep. 18, 2001, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to a semiconductor device for synchronous commutation, which executes high-frequency operation.
2. Description of the Related Art
A low-ON-resistance characteristic has conventionally been regarded as important for a DC/DC synchronous buck converter used in a computer or the like to improve the efficiency. For this reason, a trench-gate-type MOS transistor has widely been used to form a DC/DC converter. However, along with the recent rise in operation frequency, not only a low ON resistance but also a decrease in switching loss is required. Hence, it is important for a MOS transistor of a DC/DC converter to decrease not only the resistance but also the capacitance. From this viewpoint, a trench-gate-type MOS transistor is not preferable because of its structure in which a gate electrode opposes a drain layer via a thin gate insulating film. With this structure, the area can hardly be reduced, and therefore, the parasitic capacitance between the gate and the drain is large.
In place of a trench-gate-type MOS transistor, an offset-gate-type MOS transistor has begun to be used to form a DC/DC converter. The structure of a conventional offset-gate-type MOS transistor usable for a DC/DC converter has been proposed in, e.g., Malay Trivedi et al., “Comparison of RF Performance of Vertical and Lateral DMOSFET”, ISPSD99, Proceedings, pp. 245-248. Jpn. Pat. Appln. KOKAI Publication No. 5-121739 also discloses an insulated gate semiconductor device. As an example, the structure proposed by Malay et al. is shown in FIG.
1
.
FIG. 1
is a sectional view of a MOS transistor.
As shown in
FIG. 1
, an n
+
-type source region
12
, n-type LDD region
13
, n
+
-type drain region
14
, and p-type body region
15
are formed in the surface region of a p
−
-type epitaxially grown layer
11
on a p
+
-type substrate
10
. A gate electrode
16
is formed on the body region
15
between the source region
12
and the LDD region
13
. A source electrode
17
is formed on the source region and body region
15
. A drain electrode
18
is formed on the drain region
14
. A reach through layer
19
is formed to connect the source electrode
17
and substrate
10
. A source electrode
20
is formed on the lower surface of the substrate
10
.
According to the above-described structure, the source electrode
20
can be formed on the lower surface of the substrate
10
by preparing the reach through layer
19
. For this reason, the parasitic capacitance or parasitic inductance of the MOS transistor can be reduced. As a consequence, the MOS transistor can have a low resistance and can be operated at a high frequency.
However, the reach through layer
19
is most generally formed by impurity diffusion. Hence, the width of the reach through layer
19
is inevitably relatively large. In some cases, the reach through layer
19
occupies about ½ the area of the entire MOS transistor. For this reason, when the reach through layer
19
is formed, the size of the MOS transistor becomes large.
In actual manufacturing, the gate electrode
16
and source electrode
17
must be separated by a relatively large distance. This is because the misalignment of masks to be used to form the gate and source electrodes is taken into consideration. Then, the width of the body region
15
immediately under the source region
12
increases. Hence, the resistance value of the p-type body region with respect to holes becomes large, and the ruggedness to avalanche current of the MOS transistor deteriorates.
Additionally, the drain interconnection layer is normally located on the gate electrode
16
. The gate electrode
16
is adjacent to the drain electrode
18
in the horizontal direction and to the drain interconnection layer in the vertical direction. As a result, the feedback capacitance of the MOS transistor increases.
BRIEF SUMMARY OF THE INVENTION
A semiconductor device according to an aspect of the present invention comprises:
a first semiconductor region having a first conductivity type;
a second semiconductor region formed on the first semiconductor region and having the first conductivity type and a resistance higher than the first semiconductor region;
a conductive member arranged in a trench formed in the second semiconductor region and having a depth from
a surface of the second semiconductor region to the first semiconductor region;
a third semiconductor region formed in the surface of the second semiconductor region while being separated from the conductive member and having a second conductivity type;
a fourth semiconductor region formed in the surface of the second semiconductor region in a region between the conductive member and the third semiconductor region and having the second conductivity type, the fourth semiconductor region being in contact with the conductive member and being separated from the third semiconductor region; and
a gate structure formed on the fourth semiconductor region and on the second semiconductor region between the third and fourth semiconductor regions, the gate structure having one sidewall surface flush with a sidewall surface of the trench.
A semiconductor device according to other aspect of the present invention comprises:
a first semiconductor region having a first conductivity type;
second and third semiconductor regions formed in a surface of the first semiconductor region and having a second conductivity type, the second and third semiconductor regions being separated from each other;
a gate insulating film formed on the first semiconductor region between the second and third semiconductor regions;
a gate electrode formed on the gate insulating film;
first and second electrodes formed on the second and third semiconductor regions, respectively;
a dielectric interlayer formed on the first semiconductor region to cover at least the second electrode and gate electrode;
an interconnection layer formed on the dielectric interlayer immediately above at least the gate electrode and electrically connected to the first electrode; and
a first conductive film formed in the dielectric interlayer immediately above the gate electrode while being separated from the gate electrode and interconnection layer and having the same potential as that of the second electrode or a predetermined potential between the first and second electrodes.
Further, a method for fabricating a semiconductor device according to other aspect of the present invention comprises:
forming a second semiconductor region having a first conductivity type and a resistance higher than a first semiconductor region on the first semiconductor region having the first conductivity type;
forming a gate insulating film on the second semiconductor region;
forming a gate electrode on the gate insulating film;
implanting an impurity having a second conductivity type into the second semiconductor region using the gate electrode as a mask to form a third semiconductor region having the second conductivity type in a surface of the second semiconductor region;
forming an insulating film on the second semiconductor region to cover the gate electrode;
removing a partial region of the insulating film on the gate electrode;
patterning the gate electrode using the insulating film as a mask to form an opening portion reaching the gate insulating film in a partial region of the gate electrode;
implanting the impurity having the second conductivity type from the opening portion into the second semiconductor region to form the fourth semiconductor region having the second conductivity type in the surface of the second semiconductor region, the fourth semiconductor region being separated from the

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