Offset floating gate EPROM memory cell

Details Offset floating gate EPROM memory cell Offset floating gate EPROM memory cell

1986-02-18

1988-06-07

Monson, Gene M.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 41, 357 54, 357 59, 365185, H01L 2978, H01L 2702, H01L 2904, G11C 1140

Patent

active

047500247

ABSTRACT:
An electrically programmable read only memory device formed in a face of a semiconductor substrate of a first conductivity type which includes a pair of spaced apart thick oxide isolation regions defining an elongated channel of the substrate therebetween. A floating gate of conductive material overlies a portion of one of the isolation regions and a first portion of the elongated channel being separated from the oxide isolation and channel regions by an insulator layer. A control layer of conductive material extends over the channel and the floating gate separated from both of the latter by an insulator layer. Buried diffused regions are located below each oxide isolation region.

REFERENCES:
patent: 4258466 (1981-03-01), Kuo et al.
patent: 4267632 (1981-05-01), Shappir
patent: 4361847 (1982-11-01), Harari
patent: 4493057 (1985-01-01), McElroy
patent: 4561004 (1985-12-01), Kuo et al.
patent: 4597060 (1986-06-01), Mitchell et al.

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