Offset determination arrangement, offset compensation...

Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction

Reexamination Certificate

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C375S364000, C375S365000, C375S371000

Reexamination Certificate

active

08085892

ABSTRACT:
An offset determination arrangement includes a comparator device to compare an input signal with a reference value. A synchronization unit is provided to forward a comparison result of the comparator device as a function of a synchronization signal which can be generated by a synchronization clock generator. The synchronization signal includes clock pulses in which at least one clock period between adjacent clock pulses is shorter than a precedent clock period. The offset determination arrangement further includes an approximation unit to generate a compensation signal corresponding to an offset of the input signal as a function of the forwarded comparison result.

REFERENCES:
patent: 5450137 (1995-09-01), Rickard et al.
patent: 6359949 (2002-03-01), Okada et al.
patent: 7557661 (2009-07-01), Melanson et al.
patent: 2006/0089111 (2006-04-01), Mayer et al.
patent: 4109490 (1992-06-01), None
patent: WO 2006/060975 (2006-06-01), None

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