Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Input noise margin enhancement
Reexamination Certificate
2007-06-19
2007-06-19
Le, Don (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Input noise margin enhancement
C326S082000
Reexamination Certificate
active
10875086
ABSTRACT:
A receive circuit having a sampling circuit and a threshold generating circuit. The sampling circuit generates a first sample value having either a first state or a second state according whether an incoming signal exceeds a first threshold level, the first threshold level corresponding to a first threshold value. The threshold generating circuit combines a first control value and a second control value to generate the first threshold value and provides the first threshold value to the sampling circuit.
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Chen Fred F.
Garlepp Bruno W.
Ho Andrew
Stojanovic Vladimir M.
Le Don
Rambus Inc.
Shemwell Mahamedi LLP
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